KR970024168A - A MOS transistor and a method of fabricating the same - Google Patents

A MOS transistor and a method of fabricating the same Download PDF

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KR970024168A
KR970024168A KR1019950034840A KR19950034840A KR970024168A KR 970024168 A KR970024168 A KR 970024168A KR 1019950034840 A KR1019950034840 A KR 1019950034840A KR 19950034840 A KR19950034840 A KR 19950034840A KR 970024168 A KR970024168 A KR 970024168A
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film
source
gate
mos transistor
drain region
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KR1019950034840A
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KR0170513B1 (en
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유지형
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 소오스/드레인 영역과 게이트 전극과 오버랩되는 N+ 형 폴리실리콘막으로 된 버퍼층을 형성하여 후속의 Al 금속전극형성시 스파이크 현상을 방지할 수 있을 뿐만 아니라 오버랩 되는 게이트와 저농도의 드레인 영역간의 기생 캐패시턴스의 증가없이 핫캐리어 효과를 감소시킬 수 있는 모스 트랜지스터 및 그의 제조방법에 관한 것이다.The present invention forms a buffer layer of an N + type polysilicon film overlapping the source / drain region and the gate electrode to prevent spikes during subsequent formation of Al metal electrodes, as well as parasitics between overlapping gate and low concentration drain regions. The present invention relates to a MOS transistor and a method for manufacturing the same, which can reduce a hot carrier effect without increasing capacitance.

본 발명의 모스 트랜지스터는 제1도전형을 갖는 반도체 기판과, 반도체 기판상에 형성된 게이트 절연막 및 게이트와, 게이트 양측의 기판내에 형성된 LDD 구조의 제1도전형을 갖는 저농도의 소오스/드레인 영역 및 고농도의 소오스/드레인 영역과, 소오스/드레인 영역과 게이트의 표면상에 형성된 절연막과, 콘택홀을 통해 고농도의 소오스/드레인 영역과 연결되는, 산화막상에 형성된 도체막을 포함하는 것을 특징으로 한다.The MOS transistor of the present invention has a low concentration source / drain region and a high concentration having a semiconductor substrate having a first conductive type, a gate insulating film and a gate formed on the semiconductor substrate, and a first conductive type having an LDD structure formed in the substrate on both sides of the gate. And an insulating film formed on the surface of the source / drain region and the gate, and a conductor film formed on the oxide film connected to the high concentration source / drain region through the contact hole.

Description

모스 트랜지스터 및 그의 제조방법(A MOS transistor and a method of fabricating the same)A MOS transistor and a method of fabricating the same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 실시예에 따른 모스 트랜지스터의 단면도,3 is a cross-sectional view of a MOS transistor according to an embodiment of the present invention,

제4도(A) - (H)는 제3도의 모스 트랜지스터의 제조공정도.4A to 4H are manufacturing process diagrams of the MOS transistor of FIG.

Claims (13)

제1도전형을 갖는 반도체 기판(31)과, 반도체 기판상에 형성된 게이트 절연막(34) 및 게이트(35)와, 게이트 양측의 기판내에 형성된 LDD 구조의 제1도전형을 갖는 저농도의 소오스/드레인 영역(37) 및 고농도의 소오스/드레인 영역(41)과, 소오스/드레인 영역(37, 41)과 게이트(35)의 표면상에 형성된 절연막(42)과, 콘택홀을 통해 고농도의 소오스/드레인 영역(41)과 연결되는, 절연막(42)상에 형성된 도체막(44)을 포함하는 것을 특징으로 하는 모스 트랜지스터.Low concentration source / drain having a semiconductor substrate 31 having a first conductivity type, a gate insulating film 34 and a gate 35 formed on the semiconductor substrate, and a first conductivity type of an LDD structure formed in the substrate on both sides of the gate. A high concentration of source / drain is formed through the region 37 and the high concentration source / drain region 41, the insulating film 42 formed on the surfaces of the source / drain regions 37 and 41, and the gate 35. And a conductive film (44) formed on the insulating film (42) connected to the region (41). 제1항에 있어서, 절연막(42)으로 산화막이 사용되는 것을 특징으로 하는 모스 트랜지스터.The MOS transistor according to claim 1, wherein an oxide film is used as the insulating film (42). 제1항에 있어서, 도체막(44)으로 N+형 폴리실리콘막이 상용되는 것을 특징으로 하는 모스 트랜지스터.The MOS transistor according to claim 1, wherein an N + type polysilicon film is used as the conductor film. 반도체 기판(31)과, 반도체 기판(31)상에 형성된 제1도전형을 갖는 웰(32)과, 반도체 기판상에 형성된 게이트 절연막(34) 및 게이트(35)와, 게이트 양측의 기판내에 형성된 LDD 구조의 제2도전형을 갖는 저농도의 소오스/드레인 영역(37) 및 고농도의 소오스/드레인 영역(41)과, 소오스/드레인 영역(37, 41)과 게이트(35)의 표면상에 형성된 절연막(42)과, 콘택홀을 통해 고농도의 소오스/드레인 영역(41)과 연결되는, 절연막(42)상에 형성된 도체막(44)과, 기판전면상에 형성된 층간 절연막(45)과 콘택홀(46)을 통해 고농도의 소오스/드레인 영역(41)과, 연결되는, 층간 절연막(45)상에 형성된 소오스/드레인 영역(47)을 포함하는 것을 특징으로 하는 모스 트랜지스터.A semiconductor substrate 31, a well 32 having a first conductivity type formed on the semiconductor substrate 31, gate insulating films 34 and 35 formed on the semiconductor substrate, and formed in the substrates on both sides of the gate. An insulating film formed on the surface of the low concentration source / drain region 37 and the high concentration source / drain region 41 having the second conductivity type of the LDD structure, and the source / drain regions 37 and 41 and the gate 35. (42), the conductor film 44 formed on the insulating film 42, which is connected to the high concentration source / drain region 41 through the contact hole, the interlayer insulating film 45 and the contact hole formed on the front surface of the substrate ( And a source / drain region (47) formed on the interlayer insulating film (45), which is connected to the source / drain region (41) of high concentration through 46). 제1도전형을 갖는 반도체 기판(31)상에 게이트 절연막(34)과 게이트(35)를 순차 형성하는 공정과, 제2도전형을 갖는 저농도의 소오스/드레인 영역(37)과 고농도의 소오스/드레인 영역(41)을 형성하는 공정과, 게이트하부를 제외한 게이트 절연막을 식각하여 소오스/드레인 영역(37, 41)을 노출시키는 공정과, 소오스/드레인 영역(37, 41)및 게이트(35)의 노출된 표면에 절연막(42)을 형성하는 공정과, 고농도의 소오스/드레인 영역(41)상의 절연막(42)을 식각하여 콘택홀(43)을 형성하는 공정과, 기판전면에 걸쳐 도체막(44)을 증착하는 공정과, 에치백공정을 수행하여 게이트(35) 상부의 도체막(44)을 제거하는 공정과, 포토 레지스트막(57)을 도포하고 마스크를 이용하여 패터닝하는 공정과, 패터닝된 포토 레지스트막(57)을 이용하여 도체막을 식각하는 공정을 포함하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.A step of sequentially forming the gate insulating film 34 and the gate 35 on the semiconductor substrate 31 having the first conductivity type, the low concentration source / drain region 37 having the second conductivity type, and the high concentration source / Forming the drain region 41, etching the gate insulating film except the lower gate portion to expose the source / drain regions 37 and 41, and forming the drain / drain regions 37 and 41 and the gate 35. Forming an insulating film 42 on the exposed surface, etching the insulating film 42 on the source / drain region 41 at a high concentration, and forming a contact hole 43; and conductor film 44 over the entire surface of the substrate. ), A process of removing the conductor film 44 on the gate 35 by performing an etch back process, applying a photoresist film 57 and patterning the same using a mask, and Comprising etching the conductor film using the photoresist film 57 Method for producing a MOS transistor characterized in that. 제5항에 있어서, 제2도전형을 갖는 저농도 및 고농도의 소오스/드레인 영역(37), (41)을 형성하는 공정은 기판상에 포토 레지스트막(55)을 도포한 다음 제1마스크를 사용하여 패터닝하는 공정과, 패터닝된 포토 레지스트막(55)을 마스크로 하여 기판으로 제2도전형의 저농도 불순물(36)을 이온주입하여 소오스/드레인 영역(37)을 형성하는 공정과, 포토 레지스트막(55)을 제거하는 공정과, 게이트(35)의 측벽에 스페이서(39)를 형성하는 공정과, 포토 레지스트막(56)을 도포한 다음, 제2마스크를 사용하여 사용하여 패터닝하는 공정과, 패터닝된 포토 레지스트막(56)을 마스크로 하여 기판으로 제2도전형의 고농도 불순물(40)을 이온주입하여 고농도의 소오스/드레인 영역(41)을 형성하는 공정과, 포토 레지스트막(56)과 스페이서(39)를 제거하는 공정으로 이루어지는 것을 특징으로 하는 모스 트랜지스터의 제조방법.6. The process of claim 5, wherein the process of forming the low concentration and high concentration source / drain regions 37 and 41 having the second conductivity type is performed by applying the photoresist film 55 onto the substrate and then using the first mask. A step of forming a source / drain region 37 by ion implanting the second conductive type low concentration impurity 36 into the substrate using the patterning process by patterning the photoresist film 55 as a mask, and a photoresist film Removing the 55, forming the spacer 39 on the sidewall of the gate 35, applying the photoresist film 56, and then patterning using a second mask; Forming a high concentration source / drain region 41 by ion implanting the second conductive high concentration impurity 40 into the substrate using the patterned photoresist film 56 as a mask; Consisting of removing spacers 39 Method for manufacturing a MOS transistor according to claim. 제6항에 있어서, 스페이서로 질화막을 사용하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.The method of manufacturing a MOS transistor according to claim 6, wherein a nitride film is used as a spacer. 제6항에 있어서, 포토 레지스트막(55)을 제거한 후 스페이서(39)를 형성한 후에 기판상에 열산화공정을 수행하여 산화막을 200Å 의 두께로 성장시키는 공정이 추가되는 것을 특징으로 하는 모스 트랜지스터의 제조방법.7. The MOS transistor according to claim 6, further comprising a step of removing the photoresist film 55, forming a spacer 39, and then performing a thermal oxidation process on the substrate to grow the oxide film to a thickness of 200 microseconds. Manufacturing method. 제1항 또는 제6항에 있어서, 포토 레지스트막(57)을 패터닝하기 위한 마스크는 저농도 및 고농도의 소오스/드레인 영역의 이온주입용 제1 및 제2마스크와 동일한 마스크인 것을 특징으로 하는 모스 트랜지스터의 제조방법.7. The MOS transistor according to claim 1 or 6, wherein the mask for patterning the photoresist film 57 is the same mask as the first and second masks for ion implantation in the low concentration and high concentration source / drain regions. Manufacturing method. 제1항, 제6항 또는 제9항에 있어서, 포토 레지스트막(55), (56)은 포지티브 레지스트막이고, 포토 레지스트막(57)은 네가티브 포토 레지스트막인 것을 특징으로 하는 모스 트랜지스터의 제조방법.10. The MOS transistor according to claim 1, 6 or 9, wherein the photoresist films 55 and 56 are positive resist films, and the photoresist film 57 is a negative photoresist film. Way. 제1항, 제6항 또는 제9항에 있어서, 포토 레지스트막(55), (56)은 네가티브 레지스트막이고, 포토 레지스트막(57)은 포지티브 포토 레지스트막인 것을 특징으로 하는 모스 트랜지스터의 제조방법.10. The MOS transistor according to claim 1, 6 or 9, wherein the photoresist films 55 and 56 are negative resist films and the photoresist film 57 is a positive photoresist film. Way. 제1항에 있어서, 절연막(42)으로서 열 산화공정을 수행하여 산화막을 형성하는 것을 특징으로 하는 모스트랜지스터의 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein an oxide film is formed by performing a thermal oxidation process as the insulating film (42). 제12항에 있어서, 열산화공정에 의한 산화막 형성시 노출된 소오스/드레인 영역(37, 41)보다 노출된 케이트(35)의 측면에서 더 두껍게 형성되는 것을 특징으로 하는 모스 트랜지스터의 제조방법.13. The method of manufacturing a MOS transistor according to claim 12, wherein the MOS transistor is formed thicker than the exposed source / drain regions (37, 41) when the oxide film is formed by the thermal oxidation process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950034840A 1995-10-11 1995-10-11 Mos transistor and its fabrication KR0170513B1 (en)

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KR0170513B1 KR0170513B1 (en) 1999-02-01

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