KR920010954A - Manufacturing Method of MOS Transistor - Google Patents

Manufacturing Method of MOS Transistor Download PDF

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Publication number
KR920010954A
KR920010954A KR1019900019086A KR900019086A KR920010954A KR 920010954 A KR920010954 A KR 920010954A KR 1019900019086 A KR1019900019086 A KR 1019900019086A KR 900019086 A KR900019086 A KR 900019086A KR 920010954 A KR920010954 A KR 920010954A
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KR
South Korea
Prior art keywords
layer
film
gate electrode
semiconductor substrate
mos transistor
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KR1019900019086A
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Korean (ko)
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KR930011472B1 (en
Inventor
김석식
유재안
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김광호
삼성전자 주식회사
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Priority to KR1019900019086A priority Critical patent/KR930011472B1/en
Publication of KR920010954A publication Critical patent/KR920010954A/en
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Publication of KR930011472B1 publication Critical patent/KR930011472B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

내용 없음No content

Description

MOS트랜지스터의 제조방법Manufacturing Method of MOS Transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3A도 내지 제3E도는 본 발명에 의한 MOS트랜지스터의 제조공정 순서를 나타낸 단면도.3A to 3E are sectional views showing a manufacturing process procedure of the MOS transistor according to the present invention.

Claims (5)

반도체 기판상에 도포된 박막을 게이트절연연막상에 실리사이드막 및 다결정실리콘막의 이층 구조로된 폴리사이드 게이트전극을 가지는 MOS트랜지스터의 제조방법에 있어서, 반도체 기판의 표면에 상기 게이트절역막, 다결정실리콘막, 실리사이드막 및 제1절연막을 차례로 덮는 공정, 상기 제1산화막 상에 포토레지스터로된 식각 마스크 패턴을 형성하는 공정, 상기 식각마스크 패턴을사용하여 상기 제1절연막 실리사이드막 및 다결정실리콘막의 불필요한 부분을 제거하여 게이트전극을 형성하는 공정. 상기 게이트전극이 형성된 반도체기판상에 제2절연막을 침적하는 공정, 상기 침적된 제2절연막의 전면을 이방성 식각하여 상기 게이트전극의 측벽에는 스페이서를 남기는 공정, 및 상기 이방성 식각후, 상기 반도체기판을 열처리하고 상기 스페이서를 이온주입 마스크로 사용하여 반도체기판의 표면부근의 영역내에 불순물을 이온주입하는 공정을 구비한 것을 특징으로 하는 MOS 트랜지스터의 제조방법.A method of manufacturing a MOS transistor having a polyside gate electrode having a thin layer coated on a semiconductor substrate and having a two-layer structure of a silicide film and a polysilicon film on a gate insulating film, the gate switching film and the polycrystalline silicon film on the surface of the semiconductor substrate. Covering the silicide layer and the first insulating layer in sequence, forming an etch mask pattern made of a photoresist on the first oxide layer, and removing unnecessary portions of the first insulating layer silicide layer and the polysilicon layer using the etching mask pattern. Removing to form a gate electrode. Depositing a second insulating film on the semiconductor substrate on which the gate electrode is formed, anisotropically etching the entire surface of the deposited second insulating film to leave spacers on sidewalls of the gate electrode, and after the anisotropic etching, And heat-treating and implanting impurities into an area near the surface of the semiconductor substrate using the spacer as an ion implantation mask. 제1항에 있어서, 상기 제1절연막은 상기 열처리 공정으로 인한 상기 게이트전극의 실리사이드막의 균열 및 들뜸현상을 억제할 수 있을 정도의 두께를 가지는 것을 특징으로 하는 MOS트랜지스터의 제조방법.The method of claim 1, wherein the first insulating layer has a thickness sufficient to suppress cracking and lifting of the silicide layer of the gate electrode due to the heat treatment process. 제2항에 있어서, 상기 제1절연막의 두께는 500Å인 것을 특징으로 하는 MOS트랜지스터의 제조방법.The method of claim 2, wherein the first insulating layer has a thickness of 500 kV. 제1항에 있어서, 상기 스페이서를 남기는 공정에서 게이트전극이 형성되지 않은 반도체 기판상에 200Å이하의 두께를 가지도록 산화막을 남기는 것을 특징으로 하는 MOS트랜지스터의 제조방법.2. The method of manufacturing a MOS transistor according to claim 1, wherein an oxide film is left on the semiconductor substrate on which the gate electrode is not formed in a step of leaving the spacer so as to have a thickness of 200 mW or less. 제1항에 있어서, 제1절연막은 산화막인 것을 특징으로 하는 MOS트랜지스터의 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the first insulating film is an oxide film. ※ 참고사항：최초출원 내용에 의하여 공개되는 것임.※ Note: It is disclosed by the contents of the initial application.
KR1019900019086A 1990-11-23 1990-11-23 Manufacturing method of mos transistor KR930011472B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900019086A KR930011472B1 (en) 1990-11-23 1990-11-23 Manufacturing method of mos transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900019086A KR930011472B1 (en) 1990-11-23 1990-11-23 Manufacturing method of mos transistor

Publications (2)

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KR920010954A true KR920010954A (en) 1992-06-27
KR930011472B1 KR930011472B1 (en) 1993-12-08

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KR1019900019086A KR930011472B1 (en) 1990-11-23 1990-11-23 Manufacturing method of mos transistor

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970054393A (en) * 1995-12-27 1997-07-31 김주용 Transistor manufacturing method of semiconductor device
KR20210007620A (en) * 2019-07-12 2021-01-20 주식회사 대흥기전 Double field winding brushless synchronous generator removing distortion of output

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970054393A (en) * 1995-12-27 1997-07-31 김주용 Transistor manufacturing method of semiconductor device
KR20210007620A (en) * 2019-07-12 2021-01-20 주식회사 대흥기전 Double field winding brushless synchronous generator removing distortion of output

Also Published As

Publication number Publication date
KR930011472B1 (en) 1993-12-08

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