KR970052834A - Global step reduction method for semiconductor devices - Google Patents
Global step reduction method for semiconductor devices Download PDFInfo
- Publication number
- KR970052834A KR970052834A KR1019950055939A KR19950055939A KR970052834A KR 970052834 A KR970052834 A KR 970052834A KR 1019950055939 A KR1019950055939 A KR 1019950055939A KR 19950055939 A KR19950055939 A KR 19950055939A KR 970052834 A KR970052834 A KR 970052834A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- insulating layer
- insulating film
- insulating
- photoresist film
- Prior art date
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
본 발명은 반도체 소자 제조공정 중 글로벌 단차 완화 방법에 관한 것으로, 단차가 발생된 하부층 전면에 제1절연막을 형성하는 제1단계; 상기 제1절연막 상부에 감광막을 도포하여 평탄화하는 제2단계; 상대적으로 높은 단차영역의 상기 감광막을 제거하여 높은 단차영역의 상기 제1절연막을 노출시키는 제3단계; 습식식각으로 노출된 높은 단차영역의 상기 제1절연막을 식각하여 평탄화하는 제4단계 및 낮은 단차영역의 상기 감광막을 제거하는 제5단계를 포함하여 이루어지는 것을 특징으로 함으로써 별도의 장비나 공정 조건에 개발없이 간단하게 글로벌 단차를 해소할 수 있다.The present invention relates to a global step mitigation method of a semiconductor device manufacturing process, the first step of forming a first insulating film on the entire surface of the lower layer is generated step; A second step of applying a photoresist film on the first insulating film to planarize the second insulating film; A third step of exposing the first insulating film having a high stepped area by removing the photoresist film having a relatively stepped area; And a fourth step of etching and planarizing the first insulating layer of the high stepped region exposed by wet etching, and a fifth step of removing the photoresist film of the low stepped region. It is possible to solve the global step simply.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2A도 내지 제2D도는 본 발명의 일실시예에 따른 글로벌 단차 완화 과정을 나타내는 단면도.2A to 2D are cross-sectional views illustrating a global step mitigation process according to an embodiment of the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950055939A KR970052834A (en) | 1995-12-23 | 1995-12-23 | Global step reduction method for semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950055939A KR970052834A (en) | 1995-12-23 | 1995-12-23 | Global step reduction method for semiconductor devices |
Publications (1)
Publication Number | Publication Date |
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KR970052834A true KR970052834A (en) | 1997-07-29 |
Family
ID=66617020
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950055939A KR970052834A (en) | 1995-12-23 | 1995-12-23 | Global step reduction method for semiconductor devices |
Country Status (1)
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KR (1) | KR970052834A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7008755B2 (en) | 2002-07-06 | 2006-03-07 | Samsung Electronics Co., Ltd. | Method for forming a planarized layer of a semiconductor device |
-
1995
- 1995-12-23 KR KR1019950055939A patent/KR970052834A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7008755B2 (en) | 2002-07-06 | 2006-03-07 | Samsung Electronics Co., Ltd. | Method for forming a planarized layer of a semiconductor device |
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