KR960039285A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR960039285A
KR960039285A KR1019950007982A KR19950007982A KR960039285A KR 960039285 A KR960039285 A KR 960039285A KR 1019950007982 A KR1019950007982 A KR 1019950007982A KR 19950007982 A KR19950007982 A KR 19950007982A KR 960039285 A KR960039285 A KR 960039285A
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KR
South Korea
Prior art keywords
film
insulating film
forming
pattern
substrate
Prior art date
Application number
KR1019950007982A
Other languages
Korean (ko)
Other versions
KR0152919B1 (en
Inventor
박해수
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to KR1019950007982A priority Critical patent/KR0152919B1/en
Publication of KR960039285A publication Critical patent/KR960039285A/en
Application granted granted Critical
Publication of KR0152919B1 publication Critical patent/KR0152919B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

본 발명은 다층막 구조로 이루어진 고집적화된 반도체 소자 제조방법에 관한 것으로, 실리콘 기판 상에 필드 산화막을 형성하는 공정과; 상기 필드 산화막 상에 제1폴리실리콘 패턴을 형성하는 공정과; 상기 패턴이 형성된 기판 상에 층간 절연막인 고온 산화막 패턴을 형성하는 공정과; 고온 산화막 패턴이 형성된 기판 상에 제2폴리실리콘 패턴을 형성하는 공정과; 상기 패턴이 형성된 기판 전면 상에 층간 절연막으로서 불순물이 함유되지 않은 절연막을 증착하고, 단차가 낮은 부분의 매몰을 위하여 액체성의 절연막을 상기 절연막 상에 선택 증착한 후 열처리하는 공정과; BOE용액에 대해 선택식각비를 갖는 층간절연막으로서 BSG막과 BPSG막을 연속증착하는 공정과; 상기 BPSG막 상에 감광제 도포와 노광, 습식 및 건식식각을 실시하여 접촉상을 형성하는 공정 및; 접촉상이 형성된 기판 전면 사에 금속막을 증착한 후 패터닝하여 금속배선을 형성하는 공정을 구비하여 소자 제조를 완료하므로써, 접촉창 형성부의 단차로 인한 식각 공정시 발생되는 소자의 손상을 방지할 수 있을 뿐 아니라 단차가 심한 부분에는 액체성의 절연막을 선택적으로 매몰하여 금속막 잔존을 방지할 수 있게 되어 소자의 특성개선 및 수율향상을 기할 수 있는 고신뢰성의 반도체 소자를 실현할 수 있게 된다.The present invention relates to a method for manufacturing a highly integrated semiconductor device having a multilayer film structure, the method comprising: forming a field oxide film on a silicon substrate; Forming a first polysilicon pattern on the field oxide film; Forming a high temperature oxide film pattern, which is an interlayer insulating film, on the substrate on which the pattern is formed; Forming a second polysilicon pattern on the substrate on which the high temperature oxide film pattern is formed; Depositing an insulating film containing no impurities as an interlayer insulating film on the entire surface of the substrate on which the pattern is formed, and selectively depositing a liquid insulating film on the insulating film for heat treatment of a portion having a low step; Continuously depositing a BSG film and a BPSG film as an interlayer insulating film having a selective etching ratio with respect to the BOE solution; Forming a contact phase by applying a photoresist and exposing, wet and dry etching the BPSG film; Comprising a process of depositing a metal film on the front surface of the substrate on which the contact phase is formed to form a metal wiring to complete the device manufacturing, it is possible to prevent damage to the device generated during the etching process due to the step of the contact window forming step In addition, the liquid film may be prevented from remaining by selectively embedding the liquid insulating film in the stepped area, thereby realizing a highly reliable semiconductor device capable of improving the characteristics and yield of the device.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2(가)도 내지 제2(나)도는 본 발명에 따른 반도체 소자 제조방법을 도시한 단면도.2 (a) to 2 (b) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present invention.

Claims (2)

실리콘 기판 상에 필드 산화막을 형성하는 공정과; 상기 필드 산화막 상에 제1폴리실리콘 패턴을 형성하는 공정과; 상기 패턴이 형성된 기판 상에 층간 절연막인 고온 산화막 패턴을 형성하는 공정과; 고온 산화막 패턴이 형성된 기판 상에 제2폴리실리콘 패턴을 형성하는 공정과; 상기 패턴이 형성된 기판 전면 상에 층간 절연막으로서 불순물이 함유되지 않은 절연막을 증착하고, 단차가 낮은 부분의 매몰을 위하여 액체성의 절연막을 상기 절연막 상에 선택 증착한 후 열처리하는 공정과; BOE용액에 대해 선택식각비를 갖는 층간절연막으로서 BSG막과 BPSG막을 연속 증착하는 공정과; 상기 BPSG막 상에 감광제 도포와 노광, 습식 및 건식식각을 실시하여 접촉창을 형성하는 공정 및; 접촉창이 형성된 기판 전면 상에 금속막을 증착한 후 패터닝하여 금속배선을 형성하는 공정을 구비하여 이루어짐을 특징으로 하는 반도체 소자 제조방법.Forming a field oxide film on the silicon substrate; Forming a first polysilicon pattern on the field oxide film; Forming a high temperature oxide film pattern, which is an interlayer insulating film, on the substrate on which the pattern is formed; Forming a second polysilicon pattern on the substrate on which the high temperature oxide film pattern is formed; Depositing an insulating film containing no impurities as an interlayer insulating film on the entire surface of the substrate on which the pattern is formed, and selectively depositing a liquid insulating film on the insulating film for heat treatment of a portion having a low step; Continuously depositing a BSG film and a BPSG film as an interlayer insulating film having a selective etching ratio with respect to the BOE solution; Forming a contact window by applying a photoresist and exposing, wet and dry etching the BPSG film; And depositing a metal film on the entire surface of the substrate on which the contact window is formed and then patterning the metal film to form a metal wiring. 제1항에 있어서, 층간 절연막인 상기 BPSG막은 상기 BSG막보다 식각율이 더 큰 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the BPSG film, which is an interlayer insulating film, has a larger etching rate than the BSG film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950007982A 1995-04-06 1995-04-06 Method of manufacturing semiconductor KR0152919B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950007982A KR0152919B1 (en) 1995-04-06 1995-04-06 Method of manufacturing semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950007982A KR0152919B1 (en) 1995-04-06 1995-04-06 Method of manufacturing semiconductor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR2019950007982U Division KR0114699Y1 (en) 1995-04-19 1995-04-19 Door open/close device for electric oven

Publications (2)

Publication Number Publication Date
KR960039285A true KR960039285A (en) 1996-11-25
KR0152919B1 KR0152919B1 (en) 1998-12-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100417645B1 (en) * 1996-12-28 2004-04-13 주식회사 하이닉스반도체 Method for forming interlayer dielectric of semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724472B1 (en) * 2001-06-26 2007-06-04 매그나칩 반도체 유한회사 Method for forming the semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100417645B1 (en) * 1996-12-28 2004-04-13 주식회사 하이닉스반도체 Method for forming interlayer dielectric of semiconductor device

Also Published As

Publication number Publication date
KR0152919B1 (en) 1998-12-01

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