KR970023814A - Semiconductor Dry Etching Method - Google Patents

Semiconductor Dry Etching Method Download PDF

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Publication number
KR970023814A
KR970023814A KR1019950037667A KR19950037667A KR970023814A KR 970023814 A KR970023814 A KR 970023814A KR 1019950037667 A KR1019950037667 A KR 1019950037667A KR 19950037667 A KR19950037667 A KR 19950037667A KR 970023814 A KR970023814 A KR 970023814A
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KR
South Korea
Prior art keywords
etching
polycrystalline silicon
layer
layers
oxide
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KR1019950037667A
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Korean (ko)
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KR0167060B1 (en
Inventor
이강현
민경진
한민석
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김광호
삼성전자 주식회사
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Priority to KR1019950037667A priority Critical patent/KR0167060B1/en
Publication of KR970023814A publication Critical patent/KR970023814A/en
Application granted granted Critical
Publication of KR0167060B1 publication Critical patent/KR0167060B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • General Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

건식에칭공정시 사용되는 에칭가스의 가스비(Gas Ratio)을 이용한 플라즈마 에칭으로 다층막(Multi-Layer)을 인시튜(In-Situ)로 에칭하는 방법이 개시되어 있다.A method of etching a multi-layer in-situ is disclosed by plasma etching using a gas ratio of an etching gas used in a dry etching process.

산화충돌 및 다결정 실리콘층들이 순차적으로 형성되어 이루어진 다층막(Multi-Layer)의 건식 에칭방법에 있어서 단일의 에칭가스 조합으로 에칭가스의 비를 변화시켜 상기 산화층들 및 다결정 실리콘층들을 동일한 공정 챔버에서 인시튜로 에칭하는 것을 특징으로 한다.In the dry etching method of a multi-layer film in which an oxide collision and polycrystalline silicon layers are sequentially formed, the oxide layers and the polycrystalline silicon layers are recognized in the same process chamber by changing the ratio of etching gases by a single etching gas combination. It is characterized by etching in a tub.

본 발명에 따르면 실리콘 기판위에 형성되는 다결정 실리콘층과 산화층을 동일한 챔버내에서 인시튜로 에칭할 수 있는 효과가 있다.According to the present invention, the polycrystalline silicon layer and the oxide layer formed on the silicon substrate can be etched in situ in the same chamber.

Description

반도체 건식에칭방법Semiconductor Dry Etching Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2B도는 본 발명의 실시예에 의한 건식 에칭 방법을 설명하기 위해 도시된 단면도들이다.2A to 2B are cross-sectional views illustrating a dry etching method according to an embodiment of the present invention.

Claims (4)

산화층들 및 다결정 실리콘층들이 순차적으로 형성되어 이루어진 다층막(Multi-Layer)의 건식에칭방법에 있어서 에칭가스를 조합하여 상기 에칭가스의 구성비를 변화시켜 상기 산화층들 및 다결정 실리콘층들을 동일한공정 챔버에서 인시튜로 에칭하는 것을 특징으로 하는 반도체 건식에칭방법.In the dry etching method of a multi-layer film, in which oxide layers and polycrystalline silicon layers are sequentially formed, combinations of etching gases are used to change the composition ratio of the etching gases so that the oxide layers and the polycrystalline silicon layers are recognized in the same process chamber. A semiconductor dry etching method characterized in that it is etched by a tub. 제1항에 있어서, 상기 에칭가스의 조합은 불소계의 혼합가스인 것을 특징으로 하는 상기 반도체 건식에칭방법.The method of claim 1, wherein the combination of the etching gases is a fluorine-based mixed gas. 제2항에 있어서, 상기 불소계 혼합가스는 CF4와 CHF3인 것을 특징으로 하는 상기 반도체 건식 에칭 방법.The method of claim 2, wherein the fluorine-based mixed gas is CF 4 and CHF 3 . 제3항에 있어서, 상기 에칭가스의 비(CF4:CHF3)를 산화층인 실리콘 기판 직상부의 최종막질을 제외하고 그 상부에 위치한 다결정 실리콘층 및 산화층을 에칭할 때는 9:1 이상으로 하고, 상기 최종 막질인 산화층을 에칭할 때는 실리콘 기판의 선택비를 고려하여 0.9:1 내지 1.1:1로 하는 것을 특징으로 하는 상기 반도체 건식 에칭 방법.4. The etching method of claim 3, wherein the ratio of the etching gas (CF 4 : CHF 3 ) is 9: 1 or more when etching the polycrystalline silicon layer and the oxide layer positioned on the upper portion of the silicon substrate except for the final film on the silicon substrate. And 0.9: 1 to 1.1: 1 in consideration of the selectivity of the silicon substrate when etching the oxide layer which is the final film quality. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950037667A 1995-10-27 1995-10-27 Dry etching method of semiconductor KR0167060B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950037667A KR0167060B1 (en) 1995-10-27 1995-10-27 Dry etching method of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950037667A KR0167060B1 (en) 1995-10-27 1995-10-27 Dry etching method of semiconductor

Publications (2)

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KR970023814A true KR970023814A (en) 1997-05-30
KR0167060B1 KR0167060B1 (en) 1999-02-01

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100418121B1 (en) * 2001-12-22 2004-02-14 동부전자 주식회사 Method For Fabricating Semiconductor Devices
KR100460798B1 (en) * 1997-06-19 2005-05-20 삼성전자주식회사 Semiconductor device manufacturing method
KR100718072B1 (en) * 1998-09-01 2007-05-14 램 리서치 코포레이션 Techniques for forming contact holes through to a silicon layer of a substrate

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100634267B1 (en) * 2000-09-20 2006-10-16 삼성전자주식회사 Method for forming of device isolation region in a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100460798B1 (en) * 1997-06-19 2005-05-20 삼성전자주식회사 Semiconductor device manufacturing method
KR100718072B1 (en) * 1998-09-01 2007-05-14 램 리서치 코포레이션 Techniques for forming contact holes through to a silicon layer of a substrate
KR100418121B1 (en) * 2001-12-22 2004-02-14 동부전자 주식회사 Method For Fabricating Semiconductor Devices

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Publication number Publication date
KR0167060B1 (en) 1999-02-01

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