KR940016878A - Method for forming self-aligned contact of semiconductor device - Google Patents

Method for forming self-aligned contact of semiconductor device Download PDF

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Publication number
KR940016878A
KR940016878A KR1019920025881A KR920025881A KR940016878A KR 940016878 A KR940016878 A KR 940016878A KR 1019920025881 A KR1019920025881 A KR 1019920025881A KR 920025881 A KR920025881 A KR 920025881A KR 940016878 A KR940016878 A KR 940016878A
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South Korea
Prior art keywords
oxide film
layer
etching
forming
mask
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KR1019920025881A
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Korean (ko)
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KR100256798B1 (en
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이동덕
김정호
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김주용
현대전자산업 주식회사
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Publication of KR100256798B1 publication Critical patent/KR100256798B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 자기정렬 콘택 형성방법에 있어서, 워드라인 상부 및 측벽에 마스크산화막 및 스페이서산화막을 형성한 후, 전체 구조상부에 얇은 산화막, BPSG층 및 얇은 폴리실리콘층으로 적층한 다음, 콘택마스크용 감광막 패턴을 형성하고 노출된 폴리실리콘층을 식각하는 공정과, 상기 감광막 패턴을 제거하고, 폴리실리콘층을 마스크로 하고, BPSG층과 산화막간의 고식각선택비를 갖는 식각조건에서 BPSG층을 식각하는 공정과, 계속하여 산화막을 식각하여 콘택홀을 형성하는 공정을 포함하는 기술이다.In the method for forming a self-aligned contact of a semiconductor device, after forming a mask oxide film and a spacer oxide film on the word line and sidewalls, the contact layer is laminated with a thin oxide film, a BPSG layer and a thin polysilicon layer on the entire structure, and then contact Forming a photoresist pattern for a mask and etching the exposed polysilicon layer; removing the photoresist pattern, using the polysilicon layer as a mask, and etching the BPSG layer under etching conditions having a high etching selectivity between the BPSG layer and the oxide film. It is a technique including a process of etching and the process of subsequently etching an oxide film and forming a contact hole.

Description

반도체 소자의 자기정렬콘택 형성방법Method for forming self-aligned contact of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도 내지 제 6 도는 본 발명에 의해 자기정렬콘택을 형성하는 단계를 도시한 단면도.1 to 6 are cross-sectional views showing the steps of forming a self-aligned contact according to the present invention.

Claims (3)

실리콘기판 상부에 다수의 워드라인을 형성하고, 워드라인 상부 및 측벽에 마스크산화막과 스페이서산화막을 형성하는 단계와, 전체구조상부에 절연층을 증착하고 콘택영역의 절연층을 제거하여 실리콘기판이 노출된 콘택홀을 형성하는 단계와, 도전층을 전체적으로 형성하여 실리콘기판에 콘택시키는 콘택형성방법에 있어서, 워드라인 상부 및 측벽에 마스크산화막 및 스페이서산화막을 형성한 후, 전체구조상부에 얇은 산화막, BPSG층 및 얇은 폴리실리콘층으로 적충한 다음, 콘택마스크용 감광막 패턴을 형성하고 노출된 폴리실리콘층을 식각하는 공정과, 상기 감광막 패턴을 제거하고, 폴리실리콘층을 마스크로 하고, BPSG층과 산화막간의 고식각선택비를 갖는 식각조건에서 BPSG층을 식각하는 공정과, 계속하여 산화막을 식각하여 콘택홀을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 자기정렬콘택 형성방법.Forming a plurality of word lines on the silicon substrate, forming a mask oxide film and a spacer oxide film on the word lines and sidewalls, depositing an insulating layer on the entire structure, and removing the insulating layer of the contact region to expose the silicon substrate. Forming a contact hole and forming a conductive layer as a whole and contacting the silicon substrate, wherein a mask oxide film and a spacer oxide film are formed on the word line and on the sidewalls, and then a thin oxide film and a BPSG are formed on the entire structure. A layer and a thin polysilicon layer, and then forming a photoresist pattern for a contact mask and etching the exposed polysilicon layer, removing the photoresist pattern, using a polysilicon layer as a mask, and between the BPSG layer and the oxide film. Etching the BPSG layer under etching conditions having a high etching selectivity, and subsequently etching the oxide film to form contact holes; Self-aligned contact in a semiconductor device forming method comprising the step. 제 1 항에 있어서, 상기 BPSG층과 산화막간의 고식각선택비를 갖는 식각방법은 CHF3/CF4/Ar 또는 CHF3/O2혼합가스를 이용하는 것을 특징으로 하는 반도체 소자의 자기정렬콘택 형성방법.The method of claim 1, wherein the etching method having a high etching selectivity between the BPSG layer and the oxide layer uses CHF 3 / CF 4 / Ar or CHF 3 / O 2 mixed gas. . 제 2 항에 있어서, 상기 CHF3의 유량비는 50sccm 이상으로 하는 것을 특징으로 하는 반도체 소자의 자기정렬콘택 형성방법.The method of claim 2, wherein the flow rate ratio of CHF 3 is 50 sccm or more. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920025881A 1992-12-28 1992-12-28 Forming method of self-align contact of semiconductor devices KR100256798B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920025881A KR100256798B1 (en) 1992-12-28 1992-12-28 Forming method of self-align contact of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920025881A KR100256798B1 (en) 1992-12-28 1992-12-28 Forming method of self-align contact of semiconductor devices

Publications (2)

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KR940016878A true KR940016878A (en) 1994-07-25
KR100256798B1 KR100256798B1 (en) 2000-05-15

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