KR940016878A - Method for forming self-aligned contact of semiconductor device - Google Patents
Method for forming self-aligned contact of semiconductor device Download PDFInfo
- Publication number
- KR940016878A KR940016878A KR1019920025881A KR920025881A KR940016878A KR 940016878 A KR940016878 A KR 940016878A KR 1019920025881 A KR1019920025881 A KR 1019920025881A KR 920025881 A KR920025881 A KR 920025881A KR 940016878 A KR940016878 A KR 940016878A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- layer
- etching
- forming
- mask
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract 9
- 239000004065 semiconductor Substances 0.000 title claims abstract 3
- 238000005530 etching Methods 0.000 claims abstract 13
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 6
- 229920005591 polysilicon Polymers 0.000 claims abstract 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract 4
- 125000006850 spacer group Chemical group 0.000 claims abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- 229910052710 silicon Inorganic materials 0.000 claims 3
- 239000010703 silicon Substances 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 자기정렬 콘택 형성방법에 있어서, 워드라인 상부 및 측벽에 마스크산화막 및 스페이서산화막을 형성한 후, 전체 구조상부에 얇은 산화막, BPSG층 및 얇은 폴리실리콘층으로 적층한 다음, 콘택마스크용 감광막 패턴을 형성하고 노출된 폴리실리콘층을 식각하는 공정과, 상기 감광막 패턴을 제거하고, 폴리실리콘층을 마스크로 하고, BPSG층과 산화막간의 고식각선택비를 갖는 식각조건에서 BPSG층을 식각하는 공정과, 계속하여 산화막을 식각하여 콘택홀을 형성하는 공정을 포함하는 기술이다.In the method for forming a self-aligned contact of a semiconductor device, after forming a mask oxide film and a spacer oxide film on the word line and sidewalls, the contact layer is laminated with a thin oxide film, a BPSG layer and a thin polysilicon layer on the entire structure, and then contact Forming a photoresist pattern for a mask and etching the exposed polysilicon layer; removing the photoresist pattern, using the polysilicon layer as a mask, and etching the BPSG layer under etching conditions having a high etching selectivity between the BPSG layer and the oxide film. It is a technique including a process of etching and the process of subsequently etching an oxide film and forming a contact hole.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 1 도 내지 제 6 도는 본 발명에 의해 자기정렬콘택을 형성하는 단계를 도시한 단면도.1 to 6 are cross-sectional views showing the steps of forming a self-aligned contact according to the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920025881A KR100256798B1 (en) | 1992-12-28 | 1992-12-28 | Forming method of self-align contact of semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920025881A KR100256798B1 (en) | 1992-12-28 | 1992-12-28 | Forming method of self-align contact of semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940016878A true KR940016878A (en) | 1994-07-25 |
KR100256798B1 KR100256798B1 (en) | 2000-05-15 |
Family
ID=19346997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920025881A KR100256798B1 (en) | 1992-12-28 | 1992-12-28 | Forming method of self-align contact of semiconductor devices |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100256798B1 (en) |
-
1992
- 1992-12-28 KR KR1019920025881A patent/KR100256798B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100256798B1 (en) | 2000-05-15 |
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