KR960005799A - Self-aligned contact formation method of semiconductor device - Google Patents

Self-aligned contact formation method of semiconductor device Download PDF

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Publication number
KR960005799A
KR960005799A KR1019940018407A KR19940018407A KR960005799A KR 960005799 A KR960005799 A KR 960005799A KR 1019940018407 A KR1019940018407 A KR 1019940018407A KR 19940018407 A KR19940018407 A KR 19940018407A KR 960005799 A KR960005799 A KR 960005799A
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KR
South Korea
Prior art keywords
etching
self
semiconductor device
aligned contact
layer
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Application number
KR1019940018407A
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Korean (ko)
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KR100284133B1 (en
Inventor
이석희
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김주용
현대전자산업 주식회사
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Priority to KR1019940018407A priority Critical patent/KR100284133B1/en
Publication of KR960005799A publication Critical patent/KR960005799A/en
Application granted granted Critical
Publication of KR100284133B1 publication Critical patent/KR100284133B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 자기 정렬 콘택 형성 방법에 관한 것으로, 소자의 크기가 극소화 됨에 따라 사진(Photo)공정에서의 정렬오차(Misalign)등으로 인한 소자의 신뢰성 저하를 방지하기 위해 산화막과 식각 선택비가 크고 절연성이 우수한 SIPOS층을 식각 장벽(Etch Barrier)으로 사용하므로써 소자의 전기적 특성을 안정화시키고 접촉면적이 충분한 확보로 소자의 신뢰성을 향상시킬 수 있도록 한 반도체 소자의 자기 정렬 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a self-aligned contact of a semiconductor device. As the size of the device is minimized, an oxide film and an etching selectivity are increased in order to prevent reliability degradation of the device due to misalignment in a photo process. The present invention relates to a method for forming a self-aligned contact of a semiconductor device in which a large and excellent SIPOS layer is used as an etching barrier to stabilize device electrical characteristics and improve device reliability by ensuring sufficient contact area.

Description

반도체 소자의 자기정렬 콘택 형성 방법Self-aligned contact formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 내지 제1D도는 본 발명에 따른 반도체 소자의 자기정렬 콘택 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of a device for explaining a method of forming a self-aligned contact of a semiconductor device according to the present invention.

Claims (3)

반도체 소자의 자기정렬 콘택 형성 방법에 있어서, 필드 산화막(2)이 형성된 실리콘 기판(1)상에 게이트 산화막(3), 폴리 실리콘층(4) 및 산화막(5)을 순차적으로 형성한 후 사진 및 식각공정에 의해 워드라인 또는 게이트 전극(4A)을 형성한 다음 상기 워드라인 또는 게이트 전극(4A)측벽에 산화막 스페이서(7)을 형성하고 전체 상부면에 질화막(8)을 소정두께로 형성시키는 단계와 상기 단계로부터 SIPOS층(9) 및 BPSG(10)를 순차적으로 증착한 후 상기 BPSG(10)를 플로우 시키고 감광막(11)을 도포한 다음 패터닝 시키는 단계와, 상기 단계로부터 상기 SIPOS층(9)을 식각장벽으로 하여 상기 BPSG(10)를 식각한 후 상기 SIPOS층(9)을 식각하는 단계와, 상기 단계로부터 산화막과의 식각선택비 차이를 이용하여 상기 질화막(8)을 식각한후 감광막(11)을 제거시키는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 자기정렬 콘택 형성 방법.In the method for forming a self-aligned contact of a semiconductor device, the gate oxide film 3, the polysilicon layer 4, and the oxide film 5 are sequentially formed on the silicon substrate 1 on which the field oxide film 2 is formed. After the word line or gate electrode 4A is formed by an etching process, an oxide spacer 7 is formed on the sidewalls of the word line or gate electrode 4A, and the nitride film 8 is formed to a predetermined thickness on the entire upper surface. And sequentially depositing the SIPOS layer 9 and the BPSG 10 from the step, and then flowing the BPSG 10 and applying and patterning the photoresist film 11 to the SIPOS layer 9 from the step. Etching the BPSG (10) using an etch barrier, and then etching the SIPOS layer (9), and etching the nitride film (8) using the difference in etching selectivity with the oxide film from the step. 11) consists of removing steps A method of forming a self-aligned contact of a semiconductor device, characterized in that. 제1항에 있어서, 상기 SIPOS층(9)은 600 내지 800℃의 온도에서 SiH4및 N2O가스에 의해 형성되며, 내부의 산소농도는 상기 SiH4및 N2O가스비의 조절에 의해 50 내지 60%인 것을 특징으로 하는 반도체 소자의 자기정렬 콘택 형성 방법.The method of claim 1, wherein the SIPOS layer (9) is formed by SiH 4 and N 2 O gas at a temperature of 600 to 800 ℃, the internal oxygen concentration is 50 by controlling the SiH 4 and N 2 O gas ratio Self-aligned contact forming method for a semiconductor device, characterized in that from 60% to 60%. 제1항에 있어서, 상기 BPSG층(10)의 식각은 산화막 식각장비내에서 이루어지며 상기 SIPOS층(9)의 식각은 폴리 실리콘 식각장비내에서 이루어지는 것을 특징으로 하는 반도체 소자의 자기정렬 콘택 형성 방법.The method of claim 1, wherein the etching of the BPSG layer 10 is performed in an oxide etching apparatus, and the etching of the SIPOS layer 9 is performed in a polysilicon etching apparatus. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940018407A 1994-07-28 1994-07-28 Self-aligned contact formation method of semiconductor device KR100284133B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940018407A KR100284133B1 (en) 1994-07-28 1994-07-28 Self-aligned contact formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940018407A KR100284133B1 (en) 1994-07-28 1994-07-28 Self-aligned contact formation method of semiconductor device

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KR960005799A true KR960005799A (en) 1996-02-23
KR100284133B1 KR100284133B1 (en) 2001-04-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100430690B1 (en) * 1998-12-30 2004-07-27 주식회사 하이닉스반도체 Contact Forming Method of Semiconductor Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100430690B1 (en) * 1998-12-30 2004-07-27 주식회사 하이닉스반도체 Contact Forming Method of Semiconductor Device

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Publication number Publication date
KR100284133B1 (en) 2001-04-02

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