KR960026221A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR960026221A
KR960026221A KR1019940039111A KR19940039111A KR960026221A KR 960026221 A KR960026221 A KR 960026221A KR 1019940039111 A KR1019940039111 A KR 1019940039111A KR 19940039111 A KR19940039111 A KR 19940039111A KR 960026221 A KR960026221 A KR 960026221A
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KR
South Korea
Prior art keywords
forming
film
oxide film
contact hole
insulating oxide
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Application number
KR1019940039111A
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Korean (ko)
Inventor
박상훈
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940039111A priority Critical patent/KR960026221A/en
Publication of KR960026221A publication Critical patent/KR960026221A/en

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Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 반도체 제조시 콘택홀을 매립하는 텅스텐 플러그를 선택적으로 형성하는 금속배선방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a metal wiring method for selectively forming a tungsten plug for filling a contact hole during semiconductor manufacturing.

종래에는 다층 금속 배선 공정에 있어서, 에스펙트 비를 줄이는 방법의 일환으로 텅스텐-플러그를 이용하였는데, 상기 텅스텐-플러그의 경우에도 에스펙트 비가 1.5 이상이 되는 콘택홀의 깊이가 서로 다른 경우에는 문제점이 발생하고, 또한 불순물 이온주입 영역에 형성되는 콘택홀 핵 형성시 어려움이 있었다.Conventionally, in the multi-layered metal wiring process, tungsten-plug is used as a method of reducing the aspect ratio. In the case of the tungsten-plug, a problem occurs when the depths of contact holes having an aspect ratio of 1.5 or more are different. In addition, there is a difficulty in forming the contact hole nucleus formed in the impurity ion implantation region.

따라서 본 발명은 질화막을 식각 정지층으로 하여 제1콘택홀을 형성하고, 제1콘택홀 측벽에 폴리 실리콘막 스페이서를 형성하여 축소된 제2콘택홀을 형성하고, 상기 제1 및 제2콘택홀을 선택적인 텅스텐막으로 형성하여 균일도가 향상된 상태로 손쉽게 형성할 수 있어서, 반도체 소자의 신뢰성 향상이 기대된다.Accordingly, in the present invention, the first contact hole is formed using the nitride film as an etch stop layer, the polysilicon film spacer is formed on the sidewalls of the first contact hole to form a reduced second contact hole, and the first and second contact holes are formed. Can be easily formed in a state where the uniformity is improved by forming a selective tungsten film, thereby improving the reliability of the semiconductor device.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 일실시예를 나타내는 반도체 소자의 평면도.3 is a plan view of a semiconductor device showing an embodiment of the present invention.

Claims (6)

반도체 제조시의 텅스텐막을 형성함에 있어서, 실리콘기판상에 필드산화막, 게이트산화막, 게이트전극, 산화막스페이서 및 불순물 이온주입영역으로 구성된 트랜지스터를 형성하는 단계와, 전체 구조의 상부에 제1절연용 산화막, 질화막, 제2절연용 산화막을 적층하는 단계와, 사진식각법으로 제2절연용 산화막내에 제1콘택홀을 형성하는 단계와, 전체 구조의 상부에 폴리실리콘 증착 및 비등방성 식각하여 폴리실리콘 스페이서를 형성하는 단계와, 추가 식각하는 단계와, 선택적인 텅스텐막을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자 제조방법.In forming a tungsten film in semiconductor manufacturing, forming a transistor comprising a field oxide film, a gate oxide film, a gate electrode, an oxide spacer, and an impurity ion implantation region on a silicon substrate, a first insulating oxide film over the entire structure, Stacking a nitride film and a second insulating oxide film, forming a first contact hole in the second insulating oxide film by a photolithography method, depositing polysilicon and anisotropically etching the upper portion of the entire structure to form a polysilicon spacer Forming, further etching, and forming an optional tungsten film. 제1항에 있어서, 상기 질화막의 두께가 100~500Å 정도이며, 제1콘택홀 형성시 식각정지층으로 사용되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the nitride film has a thickness of about 100 to 500 μm and is used as an etch stop layer when forming the first contact hole. 제1항에 있어서, 상기 제2절연용 산화막이 제1절연용 산화막 보다 더 두껍게 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the second insulating oxide film is formed thicker than the first insulating oxide film. 제1항에 있어서, 상기 추가 식각시 질화막 및 제1절연용 산화막을 동시에 식각하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the nitride film and the first insulating oxide film are simultaneously etched during the additional etching. 제1항에 있어서, 상기 추가 식각시 노출된 제2절연용 산화막의 일부가 식각되어 폴리실리콘막 스페이서가 돌출되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein a part of the second insulating oxide layer exposed during the additional etching is etched to protrude the polysilicon layer spacer. 제1항에 있어서, 상기 선택적인 텅스텐막 형성시 돌출된 폴리실리콘막 스페이서를 감싸면서 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the forming of the selective tungsten film surrounds the protruding polysilicon film spacer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940039111A 1994-12-30 1994-12-30 Semiconductor device manufacturing method KR960026221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940039111A KR960026221A (en) 1994-12-30 1994-12-30 Semiconductor device manufacturing method

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Application Number Priority Date Filing Date Title
KR1019940039111A KR960026221A (en) 1994-12-30 1994-12-30 Semiconductor device manufacturing method

Publications (1)

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KR960026221A true KR960026221A (en) 1996-07-22

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100458464B1 (en) * 1997-12-30 2005-02-05 주식회사 하이닉스반도체 Method for forming contact of semiconductor device to compensate for misalignment in contact hole patterning process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100458464B1 (en) * 1997-12-30 2005-02-05 주식회사 하이닉스반도체 Method for forming contact of semiconductor device to compensate for misalignment in contact hole patterning process

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