KR960026221A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- KR960026221A KR960026221A KR1019940039111A KR19940039111A KR960026221A KR 960026221 A KR960026221 A KR 960026221A KR 1019940039111 A KR1019940039111 A KR 1019940039111A KR 19940039111 A KR19940039111 A KR 19940039111A KR 960026221 A KR960026221 A KR 960026221A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- film
- oxide film
- contact hole
- insulating oxide
- Prior art date
Links
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 반도체 제조시 콘택홀을 매립하는 텅스텐 플러그를 선택적으로 형성하는 금속배선방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a metal wiring method for selectively forming a tungsten plug for filling a contact hole during semiconductor manufacturing.
종래에는 다층 금속 배선 공정에 있어서, 에스펙트 비를 줄이는 방법의 일환으로 텅스텐-플러그를 이용하였는데, 상기 텅스텐-플러그의 경우에도 에스펙트 비가 1.5 이상이 되는 콘택홀의 깊이가 서로 다른 경우에는 문제점이 발생하고, 또한 불순물 이온주입 영역에 형성되는 콘택홀 핵 형성시 어려움이 있었다.Conventionally, in the multi-layered metal wiring process, tungsten-plug is used as a method of reducing the aspect ratio. In the case of the tungsten-plug, a problem occurs when the depths of contact holes having an aspect ratio of 1.5 or more are different. In addition, there is a difficulty in forming the contact hole nucleus formed in the impurity ion implantation region.
따라서 본 발명은 질화막을 식각 정지층으로 하여 제1콘택홀을 형성하고, 제1콘택홀 측벽에 폴리 실리콘막 스페이서를 형성하여 축소된 제2콘택홀을 형성하고, 상기 제1 및 제2콘택홀을 선택적인 텅스텐막으로 형성하여 균일도가 향상된 상태로 손쉽게 형성할 수 있어서, 반도체 소자의 신뢰성 향상이 기대된다.Accordingly, in the present invention, the first contact hole is formed using the nitride film as an etch stop layer, the polysilicon film spacer is formed on the sidewalls of the first contact hole to form a reduced second contact hole, and the first and second contact holes are formed. Can be easily formed in a state where the uniformity is improved by forming a selective tungsten film, thereby improving the reliability of the semiconductor device.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명의 일실시예를 나타내는 반도체 소자의 평면도.3 is a plan view of a semiconductor device showing an embodiment of the present invention.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940039111A KR960026221A (en) | 1994-12-30 | 1994-12-30 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940039111A KR960026221A (en) | 1994-12-30 | 1994-12-30 | Semiconductor device manufacturing method |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960026221A true KR960026221A (en) | 1996-07-22 |
Family
ID=66647694
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940039111A KR960026221A (en) | 1994-12-30 | 1994-12-30 | Semiconductor device manufacturing method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960026221A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100458464B1 (en) * | 1997-12-30 | 2005-02-05 | 주식회사 하이닉스반도체 | Method for forming contact of semiconductor device to compensate for misalignment in contact hole patterning process |
-
1994
- 1994-12-30 KR KR1019940039111A patent/KR960026221A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100458464B1 (en) * | 1997-12-30 | 2005-02-05 | 주식회사 하이닉스반도체 | Method for forming contact of semiconductor device to compensate for misalignment in contact hole patterning process |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR970003718A (en) | How to Form a Morse Field Effect Transistor | |
KR960043267A (en) | Improved Manufacturing Method of Inverse Tee (T) Transistor | |
KR900019155A (en) | Contact Formation Method Using Etch Barrier | |
JPH05206451A (en) | Mosfet and its manufacture | |
KR970077674A (en) | Manufacturing method of semiconductor integrated circuit device | |
KR940012647A (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
JPH04275436A (en) | Soimos transistor | |
KR960026221A (en) | Semiconductor device manufacturing method | |
JPH1197529A (en) | Manufacture of semiconductor device | |
KR970003468A (en) | Contact hole formation method of semiconductor device | |
KR0140733B1 (en) | Method of forming dontact in semiconductor device | |
KR960006339B1 (en) | Fabricating method of semiconductor device | |
KR950021753A (en) | Method for manufacturing field effect semiconductor device | |
KR0183018B1 (en) | Filling method for contact hole of semiconductor device | |
KR20010073705A (en) | Method for forming a contact of a semiconductor device using a selective epitaxial growth | |
KR19980037660A (en) | Wiring of Semiconductor Devices and Manufacturing Method Thereof | |
KR960026181A (en) | Plug Formation Method | |
KR20070067441A (en) | Method of fabricating transistor in stacked cell | |
KR20020048266A (en) | Method for manufacturing a semiconductor device | |
KR950021724A (en) | Method for manufacturing field effect semiconductor device | |
KR970003520A (en) | Contact hole formation method of a fine semiconductor device | |
KR970003613A (en) | Transistor Formation Method of Semiconductor Device | |
KR970003464A (en) | Method of forming fine contact hole in semiconductor device | |
KR950021428A (en) | Semiconductor device and manufacturing method thereof | |
KR950021245A (en) | Semiconductor device manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |