KR960026181A - Plug Formation Method - Google Patents

Plug Formation Method Download PDF

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Publication number
KR960026181A
KR960026181A KR1019940037498A KR19940037498A KR960026181A KR 960026181 A KR960026181 A KR 960026181A KR 1019940037498 A KR1019940037498 A KR 1019940037498A KR 19940037498 A KR19940037498 A KR 19940037498A KR 960026181 A KR960026181 A KR 960026181A
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KR
South Korea
Prior art keywords
forming
film
contact hole
insulating film
plug
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Application number
KR1019940037498A
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Korean (ko)
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KR100369341B1 (en
Inventor
박상훈
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김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940037498A priority Critical patent/KR100369341B1/en
Publication of KR960026181A publication Critical patent/KR960026181A/en
Application granted granted Critical
Publication of KR100369341B1 publication Critical patent/KR100369341B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 금속막 콘택 홀을 형성하되 콘택홀 측벽에 플러그 물질이 선택적으로 증착되는 물질막을 성장시키는 단계; 플러그 물질을 선택적으로 형성하여 콘택홀을 완전히 매립하는 단계를 포함하는 것을 특징으로 하는 플러그 형성방법에 관한 것으로, 고집적화로 인해 에스펙트 비가 큰 콘택홀에 텅스텐 플러그를 균일도가 향상된 상태로 손쉽게 형성함으로써 반도체 소자의 신뢰성 향상 및 고집적화를 앞당기는 효과가 있다.The present invention provides a method of forming a metal contact hole, the method comprising: growing a material film in which a plug material is selectively deposited on a sidewall of the contact hole; A method of forming a plug, the method comprising: selectively forming a plug material to completely fill a contact hole, wherein the plug forming method includes a semiconductor by easily forming a tungsten plug with improved uniformity in a contact hole having a high aspect ratio due to high integration. There is an effect of improving the reliability and high integration of the device.

Description

플러그 형성방법Plug Formation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명의 일 실시예에 따른 플러그 형성 공정도.2A to 2C are plug process steps according to one embodiment of the present invention.

Claims (6)

금속막 콘택 홀을 형성하되 콘택홀 측벽에 플러그 물질이 선택적으로 중착되는 물질막을 성장시키는 단계; 플러그 물질을 선택적으로 형성하여 콘택홀을 완전히 매립하는 단계를 포함하는 것을 특징으로 하는 플러그 형성방법.Forming a metal film contact hole, wherein the material film is selectively grown on the sidewalls of the contact hole; Selectively forming a plug material to completely fill the contact holes. 제1항에 있어서; 상기 금속막 콘택 홀을 형성하되 콘택홀 측벽에 플러그 물질이 선택적으로 증착되는 물질막을 성장시키는 단계는; 금속막이 접속될 하부전도층상에 제1절연막을 형성하는 단계; 상기 제1절연막 상에 제2절연막을 형성하는 단계; 상기 제2절연막 상에 제2절연막과 식각선택비를 갖는 제3절연막을 형성하는단계; 콘택 마스크를 형성하고 상기 제3절연막을 식각하는 단계; 상기 콘택마스크를 이온주입장벽으로 하여 Ar 이온을 이온주입하는 단계; 상기 제3절연막이 식각된 부위의 측벽에 플러그 물질이 선택적으로 증착되는물질막을 형성하는 단계; 노출된 제2절연막 및 아르곤 이온주입에 의해 손상받은 상기 제1절연막을 식각하여 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 하는 플러그 형성방법.The method of claim 1; Forming a metal layer contact hole and growing a material layer in which a plug material is selectively deposited on a sidewall of the contact hole; Forming a first insulating film on the lower conductive layer to which the metal film is to be connected; Forming a second insulating film on the first insulating film; Forming a third insulating layer having an etch selectivity with a second insulating layer on the second insulating layer; Forming a contact mask and etching the third insulating layer; Implanting Ar ions using the contact mask as an ion implantation barrier; Forming a material film on which a plug material is selectively deposited on a sidewall of the portion where the third insulating film is etched; And etching the exposed second insulating film and the first insulating film damaged by argon ion implantation to form a contact hole. 제2항에 있어서, 상기 제1절연막 및 제3절연막은 산화막인 것을 특징으로 하는 플러그 형성방법.The method of claim 2, wherein the first insulating film and the third insulating film are oxide films. 제3항에 있어서, 상기 제2절연막은 질화막인 것을 특징으로 하는 플러그 형성방법.4. The plug forming method according to claim 3, wherein the second insulating film is a nitride film. 제1항에 있어서, 상기 플러그 물질은 텅스텐인 것을 특징으로 하는 플러그 형성방법.The method of claim 1 wherein the plug material is tungsten. 제1항에 있어서, 상기 플러그 물질이 선택적으로 증착되는 물질막은 폴리실리콘막인 것을 특징으로 하는 플러그 형성방법.The method of claim 1, wherein the material film on which the plug material is selectively deposited is a polysilicon film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940037498A 1994-12-27 1994-12-27 Manufacturing method of semiconductor device for forming plug KR100369341B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940037498A KR100369341B1 (en) 1994-12-27 1994-12-27 Manufacturing method of semiconductor device for forming plug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940037498A KR100369341B1 (en) 1994-12-27 1994-12-27 Manufacturing method of semiconductor device for forming plug

Publications (2)

Publication Number Publication Date
KR960026181A true KR960026181A (en) 1996-07-22
KR100369341B1 KR100369341B1 (en) 2003-03-26

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KR1019940037498A KR100369341B1 (en) 1994-12-27 1994-12-27 Manufacturing method of semiconductor device for forming plug

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102343470B1 (en) 2016-01-28 2021-12-24 삼성전자주식회사 Semiconductor device and method for fabricating the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62243325A (en) * 1986-04-15 1987-10-23 Matsushita Electric Ind Co Ltd Manufacture of semiconductor integrated circuit
JPH01286328A (en) * 1988-05-11 1989-11-17 Nec Corp Contact hole burying method

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