KR960026215A - How to Form Contact Holes - Google Patents

How to Form Contact Holes Download PDF

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Publication number
KR960026215A
KR960026215A KR1019940039103A KR19940039103A KR960026215A KR 960026215 A KR960026215 A KR 960026215A KR 1019940039103 A KR1019940039103 A KR 1019940039103A KR 19940039103 A KR19940039103 A KR 19940039103A KR 960026215 A KR960026215 A KR 960026215A
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KR
South Korea
Prior art keywords
oxide film
film
dry etching
forming
nitride film
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Application number
KR1019940039103A
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Korean (ko)
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KR100290770B1 (en
Inventor
박상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019940039103A priority Critical patent/KR100290770B1/en
Publication of KR960026215A publication Critical patent/KR960026215A/en
Application granted granted Critical
Publication of KR100290770B1 publication Critical patent/KR100290770B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 콘택 홀 형성방법에 관한 것으로서, 특히 질화막에 의한 종말점 건식식각 및 아르곤 원자의 이온주입을 실시하여 스텝 커버리지를 개선할 수 있는 콘택 홀 형성방법에 관한 것으로서, 소정의 전도체 상부에 제1산화막, 질화막 및 제2산화막을 적층하는 단계, 소정의 감광막 패턴을 형성하는 단계, 습식식각 하는 단계, 제1차 건식식각하는 단계, 불순물을 이온주입하는 단계, 상기 감광막 패턴을 제거하는 단계 및 제2차 건식식각하는 단계로 이루어져서, 제2산화막에 형성된 예리한 돌기부를 곡률형상으로 만들어 이후에 형성되는 금속 배선막이 협착 또는 단락되는 형상을 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole capable of improving step coverage by performing end point dry etching using a nitride film and ion implantation of argon atoms, and on a predetermined conductor. Stacking a first oxide film, a nitride film, and a second oxide film, forming a predetermined photoresist pattern, wet etching, first dry etching, implanting impurities, and removing the photoresist pattern And a second dry etching step, thereby making the sharp protrusion formed in the second oxide film into a curvature shape to prevent a shape in which the metal wiring film formed thereafter is narrowed or short-circuited.

Description

콘택 홀 형성방법How to Form Contact Holes

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (8)

소정의 전도체 상부에 제1산화막, 질화막 및 제2산화막을 적층하는 단계, 소정의 감광막 패턴을 형성하여 상기 질화막을 식각 정지층으로 하여 습식식각 및 제1차 건식식각을 순차적으로 실시하는 단계, 상기 제1산화막에 불순물을 이온주입하는 단계, 상기 감공막 패턴을 제거하는 단계 및 상기 제1산화막과 질화막을 제2차 건식식각하는 단계로 이루어진 콘택 홀 형성방법.Stacking a first oxide film, a nitride film, and a second oxide film on a predetermined conductor, forming a predetermined photoresist pattern, and sequentially performing wet etching and first dry etching using the nitride film as an etch stop layer; A method of forming a contact hole comprising ion implanting impurities into a first oxide film, removing the air gap pattern, and second dry etching of the first oxide film and the nitride film. 제1항에 있어서, 상기 제1산화막은 800 내지 1,200Å정도의 두께의 TEOS막인 것을 특징으로 하는 콘택홀 형성방법.The method of claim 1, wherein the first oxide film is a TEOS film having a thickness of about 800 to 1,200 μs. 제1항에 있어서, 상기 제2산화막은 4,500 내지 5,500Å정도의 두께의 BPSG막인 것을 특징으로 하는 콘택홀 형성방법.The method of claim 1, wherein the second oxide film is a BPSG film having a thickness of about 4,500 to 5,500 GPa. 제1항에 있어서, 상기 질화막은 50 내지 500Å정도의 두께로 형성하는 것을 특징으로 하는 콘택 홀 형성방법.The method of claim 1, wherein the nitride film is formed to a thickness of about 50 to 500 kPa. 제1항 내지 제4항 중 어느 한 항에 있어서, 상기 제1차 건식식각 단계시에 상기 질화막을 식각 정지층으로 사용하여 상기 제2산화막을 종말점 식각하는 것을 특징으로 하는 콘택 홀 형성방법.The method of claim 1, wherein the second oxide layer is endpoint-etched using the nitride layer as an etch stop layer during the first dry etching step. 6. 제1항 내지 제4항 중 어느 한 항에 있어서, 상기 제1,2차 건식식각은 CF4, CHF3, He, Ar 및 O2의 혼합가스를 이용해서 식각하는 것을 특징으로 하는 콘택 홀 형성방법.The method of claim 1, wherein the first and second dry etchings are etched using a mixed gas of CF 4 , CHF 3 , He, Ar, and O 2 . Way. 제1항 내지 제4항 중 어느 한 항에 있어서, 상기 불순물은 아르곤 원자인 것을 특징으로 하는 콘택 홀 형성방법.The contact hole forming method according to any one of claims 1 to 4, wherein the impurity is an argon atom. 제7항에 있어서, 상기 아르곤 원자는 30~200kev, 1×1012~1×1018원자/㎠의 조건으로 이온주입하는 것을 특징으로 하는 콘택 홀 형성방법.8. The method of claim 7, wherein the argon atoms are ion implanted under the conditions of 30 to 200 kev and 1 x 10 12 to 1 x 10 18 atoms / cm 2. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940039103A 1994-12-30 1994-12-30 Method for forming contact hole KR100290770B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940039103A KR100290770B1 (en) 1994-12-30 1994-12-30 Method for forming contact hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940039103A KR100290770B1 (en) 1994-12-30 1994-12-30 Method for forming contact hole

Publications (2)

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KR960026215A true KR960026215A (en) 1996-07-22
KR100290770B1 KR100290770B1 (en) 2001-06-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110911281A (en) * 2019-11-29 2020-03-24 中芯集成电路制造(绍兴)有限公司 Semiconductor device having trench type gate and method of manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100477823B1 (en) * 1997-12-27 2005-06-29 주식회사 하이닉스반도체 Contact hole formation method of semiconductor device
KR20170022516A (en) 2015-08-21 2017-03-02 박영찬 Seed culture for soybean sauce and preparation method of soybean sauce using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110911281A (en) * 2019-11-29 2020-03-24 中芯集成电路制造(绍兴)有限公司 Semiconductor device having trench type gate and method of manufacturing the same
CN110911281B (en) * 2019-11-29 2022-07-29 绍兴中芯集成电路制造股份有限公司 Semiconductor device having trench type gate and method of manufacturing the same

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