KR100223774B1 - Process for fabricating semicondcutor device with fine contact hole - Google Patents
Process for fabricating semicondcutor device with fine contact hole Download PDFInfo
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- KR100223774B1 KR100223774B1 KR1019960069248A KR19960069248A KR100223774B1 KR 100223774 B1 KR100223774 B1 KR 100223774B1 KR 1019960069248 A KR1019960069248 A KR 1019960069248A KR 19960069248 A KR19960069248 A KR 19960069248A KR 100223774 B1 KR100223774 B1 KR 100223774B1
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- silicon substrate
- contact hole
- oxide film
- field oxide
- ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조 방법.Semiconductor device manufacturing method.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
콘택홀 형성시 필드산화막이 깍여 나간 부위에 플러그 이온주입이 용이하도록하여 접합 누설을 방지하고자 함.When forming the contact hole, it is to prevent the leakage of the junction by facilitating the plug ion implantation in the part where the field oxide film is cut off.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
콘택홀 형성시 스페이스 마진 부족 및 마스크 작업시 미스 얼라인으로 인해 필드 산화막이 깍여 나갔을 때, 인-시튜로 콘택홀 안의 실리콘 기판, 특히 필드산화막이 깍여나가 뾰족하게 튀어 나와있는 실리콘 기판의 모서리 부분을 살짝 등방성 식각하여, 이 부위에서 플러그 이온주입이 용이하게 한다.When the field oxide film is cut out due to lack of space margin in contact hole formation and misalignment during masking, in-situ cuts the edges of the silicon substrate in the contact hole, especially the silicon substrate where the field oxide film is cut out. It is slightly isotropically etched to facilitate plug ion implantation at this site.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치Semiconductor devices
Description
본 발명은 미세 콘택홀 형성을 위한 반도체 장치 제조 방법에 관한 것으로, 콘택홀 형성시 층간산화막 식각으로 드러난 실리콘 기판을 인-시튜(In-Situ)로 등방성 식각하여, 후속 공정인 플러그(Plug) 이온주입을 용이하게 하는 반도체 장치 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device for forming a fine contact hole, and to form isotropic etching of the silicon substrate exposed by the interlayer oxide etching during the formation of the contact hole in-situ, the plug ions which are subsequent processes A semiconductor device manufacturing method for facilitating implantation.
반도체 소자의 고집적화로 인하여 칩(Chip)내의 패턴간의 스페이스가 점점 줄어 들고 있다.Due to the high integration of semiconductor devices, the space between patterns in the chip is gradually decreasing.
따라서, 256M DRAM 급 이상의 소자에서는 필드산화막 형성시 발생되는 버즈빅(BIRD'S BEAK)으로 소자의 활설영역 확보가 어려워지고 있다. 따라서, 256M DRAM 급 이상의 소자에서는 R-LOCOS와 같이 변형된 소자분리 기술을 사용하고 있으나, 이 공정은 버즈빅이 거의 발생하지 않기 때문에 활성영역 확보에는 유리한 반면, 후속 공정에서 콘택홀 형성시 마스크 공정 작업의 한계 또는 미스 얼라인(Miss-Align)으로 인해 필드산화막이 깍이는 문제가 발생이 된다. 이 경우 필드산화막이 깍인 실리콘 기판 표면은 활성영역이 아니기 때문에 누설전류를 방지하기 위한 플러그 이온주입 공정을 진행하게 되는데, 이때 필드산화막이 깍인 부위는 공간이 너무 작아 불순물 이온이 주입이 되지 않는 문제점이 존재한다.Therefore, it is difficult to secure the active area of the device due to the BIRD'S BEAK generated when the field oxide film is formed in the device of 256M DRAM class or more. Therefore, the modified device isolation technology such as R-LOCOS is used in devices of 256M DRAM or higher, but this process is advantageous for securing the active area because hardly any buzz is generated, whereas in the subsequent process, a mask process is formed during contact hole formation. Due to the limitation of work or miss-alignment, the problem of field oxide film cutting is caused. In this case, since the surface of the silicon substrate where the field oxide film is cut is not an active region, the plug ion implantation process is performed to prevent leakage current. In this case, the area where the field oxide film is cut is so small that impurity ions cannot be implanted. exist.
도면 도 1a 내지 도 1g를 통하여 종래기술의 문제점을 설명하기로 한다.The problem of the prior art will be described with reference to FIGS. 1A to 1G.
먼저, 도 1a는 실리콘 기판(11)상에 R-LOCOS 방법으로 필드산화막(12)을 형성한 다음, 게이트(도시않됨) 및 접합(10), 제1층간절연막(13), 비트라인(14)을 각각 형성한 다음, 제2층간절연막(15)을 증착하고 콘택마스크 패턴(16)을 형성한 상태의 단면도이다.First, FIG. 1A shows the field oxide film 12 formed on the silicon substrate 11 by the R-LOCOS method, followed by a gate (not shown) and a junction 10, a first interlayer insulating film 13, and a bit line 14. ), And a second interlayer insulating film 15 is deposited, and a contact mask pattern 16 is formed.
이어서, 도 1b와 같이, 콘택 마스크 패턴(16)을 식각 마스크로 하여 층간절연막(15, 13)을 비등방성 식각하여 콘택홀을 형성한 다음, 콘택 마스크 패턴(16)을 제거하는데, 이때, 도면의 A와 같이 콘택 마스크 패턴 작업시 미스 얼라인으로 인해 필드산화막 가장자리가 식각되는 문제가 발생되는데, 이때 필드산화막 하부의 실리콘 기판이 노출되어 후속 공정의 전도체 박막 증착시 누설전류가 발생되는 문제점이 있다.Subsequently, as shown in FIG. 1B, the contact hole is formed by anisotropically etching the interlayer insulating layers 15 and 13 using the contact mask pattern 16 as an etch mask, and then removing the contact mask pattern 16. As shown in A, the edge of the field oxide layer is etched due to the misalignment when the contact mask pattern is being worked on. In this case, the silicon substrate under the field oxide layer is exposed, so that a leakage current is generated when the conductor thin film is deposited in a subsequent process. .
이어서, 도 1c는 플러그 이온주입(17) 공정을 진행하는 단면도이다. 여기서, 플러그 이온주입 공정의 목적은 접합을 형성하여 접합 누설전류와 리프레쉬 특성을 개선하기 위하여 저농도 도핑 영역을 형성하는 것이다.1C is a cross-sectional view of the plug ion implantation 17 process. Here, the purpose of the plug ion implantation process is to form a lightly doped region in order to form a junction to improve junction leakage current and refresh characteristics.
도 1d는 상기 공정 진행후에 A와 같이 필드산화막(12)이 깍인 부위의 공간이 너무 좁아 이 부위는 이온주입이 되지 못해 실리콘 기판이 그대로 노출되어 있음을 도시한다.FIG. 1D shows that the silicon substrate is exposed as it is because the space of the portion where the field oxide film 12 is cut is too narrow as in A after the process is performed, and the region cannot be ion implanted.
이어서, 도 1e와 같이 스페이스용 산화막(18)을 증착하고, 도 1f와 같이 마스크 없이 전면식각하여 콘택홀 측벽에 스페이서 산화막(18)을 형성한다.Subsequently, a space oxide film 18 is deposited as shown in FIG. 1E, and a spacer oxide film 18 is formed on the sidewalls of the contact holes by etching the entire surface without a mask as shown in FIG. 1F.
도 1g는 상기 공정 진행후에 폴리실리콘막(19)을 증착한 상태의 단면도로서, 이 경우 A와 같이 폴리 실리콘 박막과 실리콘 기판의 거리가 너무 가까워 접합 누설의 문제가 존재함을 알수가 있다.FIG. 1G is a cross-sectional view of the polysilicon film 19 deposited after the above process. In this case, the distance between the polysilicon thin film and the silicon substrate is too close as in A. Thus, there is a problem of junction leakage.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로, 콘택홀 형성시 필드산화막이 깍여 나간 부위에 플러그 이온주입이 용이하도록하여 접합 누설을 방지하는 반도체 장치 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device to prevent the leakage of the junction to facilitate the plug ion implantation in the portion of the field oxide film is cut off when forming the contact hole.
도 1a지 도 1g 종래기술에 따른 미세 콘택홀 형성 공정도,Figure 1a to Figure 1g fine contact hole forming process according to the prior art,
도 2a내지 도 2g 본 발명의 일실시예에 따른 미세 콘택홀 형성 공정도.2A to 2G are fine contact hole forming process diagrams according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20 : 접합 21 : 실리콘 기판20: junction 21: silicon substrate
22 : 필드산화막 23 : 제1층간절연막22: field oxide film 23: first interlayer insulating film
24 : 비트라인 25 : 제2층간절연막24 bit line 25 second interlayer insulating film
26 : 콘택 마스크 패턴 27 : 스페이서 산화막26 contact mask pattern 27 spacer oxide film
28 : 스페이서 산화막 29 : 폴리실리콘막28 spacer oxide film 29 polysilicon film
본 발명의 반도체 장치 제조 방법은 반도체 기판 상의 층간절연막을 선택식각하여 콘택홀을 형성하고, 인-시튜로 노출된 실리콘 기판 표면을 등방성 식각하는 단계, 및 상기 콘택홀에 의해 노출된 실리콘 기판 표면에 플러그 이온주입을 실시하는 단계를 포함하여 이루어진다.In the method of manufacturing a semiconductor device of the present invention, a method of forming a contact hole by selectively etching an interlayer insulating film on a semiconductor substrate, and isotropically etching the silicon substrate surface exposed in-situ, and on the silicon substrate surface exposed by the contact hole Performing a plug ion implantation.
도 2a 내지 도 2g는 본 발명의 일실시예에 따른 반도체 장치 제조 공정도로서, 이를 참조하여 본 발명을 상세히 설명한다.2A to 2G are diagrams illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention, and the present invention will be described in detail with reference to the drawings.
먼저, 도 2a는 실리콘 기판(21)상에 필드산화막(22)을 형성한 다음, 게이트(도시않됨) 및 접합(20), 제1층간절연막(23), 비트라인(24)을 각각 형성한 다음, 제2층간절연막(25)을 증착하고 콘택 마스크 패턴(26)을 형성한 상태이다.First, FIG. 2A shows that a field oxide film 22 is formed on a silicon substrate 21, and then a gate (not shown) and a junction 20, a first interlayer insulating film 23, and a bit line 24 are formed. Next, the second interlayer insulating film 25 is deposited and the contact mask pattern 26 is formed.
이어서, 도 2b와 같이 콘택 마스크 패턴(26)을 식각 마스크로 하여 층간산화막(25,23)을 비등방성 식각하여 콘택홀을 형성한 후, 인-시튜로 실리콘 기판(21)을 등방성 식각하여, 도면의 B와 같이 필드산화막(22)이 깍여 노출된 실리콘 기판의 모서리 부분이 완만지도록 한다.Subsequently, as shown in FIG. 2B, anisotropic etching of the interlayer oxide layers 25 and 23 is performed using the contact mask pattern 26 as an etching mask to form contact holes, and then the silicon substrate 21 is isotropically etched in-situ. As shown in FIG. 2B, the edge portion of the exposed silicon substrate is smoothed by cutting the field oxide film 22.
이때, 등방성 식각은 CF4/O2또는 SF6/Cl2가스를 사용한 등방성 건식식각을 이용하며, CF4/O2를 사용할 경우, 1800∼2800W 소오스 파워, 100∼800W 바이어스 파워, 10∼50sccm CF4,5∼100sccm O2, 5∼200mTorr 압력의 공정 조건에서 등방성 식각을 실시하고, SF6/Cl2가스를 사용할 경우, 1800∼2800W 소오스 파워, 100∼500W 바이어스 파워, 10∼50sccm SF6, 5∼50sccm Cl2,5∼200mTorr 압력의 공정 조건에서 이루어진다.At this time, the isotropic etching is an isotropic dry etching using CF 4 / O 2 or SF 6 / Cl 2 gas, when using CF 4 / O 2 1800 ~ 2800W source power, 100 ~ 800W bias power, 10 ~ 50sccm When isotropic etching is performed under CF 4 , 5 to 100 sccm O 2 and 5 to 200 mTorr pressure, and SF 6 / Cl 2 gas is used, 1800 to 2800 W source power, 100 to 500 W bias power, and 10 to 50 sccm SF 6 , 5 to 50 sccm Cl 2 , and 5 to 200 mTorr under pressure.
이어서, 도 2c는 플러그 이온주입을 실시한 상태로서, 도 2d에 도시된 바와같이 필드산화막인 깍인 부위의 실리콘기판의 모양이 완만 하므로, 이 부위의 플러그 이온주입이 용이하여 도면의 C와 같이 실리콘 기판에 플러그 이온주입영역(저농도 불순물 영역)이 형성된다.Subsequently, FIG. 2C is a state in which the plug ion implantation is performed, and as shown in FIG. 2D, since the shape of the silicon substrate in the shaved portion of the field oxide film is gentle, the plug ion implantation in this region is easy, and the silicon substrate as shown in FIG. The plug ion implantation region (low concentration impurity region) is formed.
이어서, 도 2e와 같이 스페이스용 산화막(28)을 증착하고, 도 2f와 같이 마스크 없이 전면식각하여 콘택홀 측벽에 스페이서 산화막(28)을 형성한다. 도 2g는 상기 공정 진행후에 폴리실리콘막(29)을 증착한 상태의 단면도로서, 도면의 C와 같이 폴리실리콘막(29)과 접합하부의 실리콘 기판 사이의 마진이 충분하여 접합 누설의 문제를 방지하게 된다.Subsequently, a space oxide film 28 is deposited as shown in FIG. 2E, and a spacer oxide film 28 is formed on the sidewalls of the contact holes by etching the entire surface without a mask as shown in FIG. 2F. FIG. 2G is a cross-sectional view of the polysilicon film 29 deposited after the above process. As shown in FIG. C, a margin between the polysilicon film 29 and the silicon substrate under the junction is sufficient to prevent a problem of junction leakage. Done.
상기한 바와같이 본 발명은 256M DRAM 급 이상 반도체 소자의 콘택홀 형성시, 콘택 식각후 인-시튜로 노출된 실리콘 기판을 등방성 식각하여 필드산화막이 깍인 실리콘 기판을 완만하게 만들어줌으로, 추후 플러그 이온주입시 필드산화막이 깍인 실리콘 기판에 불순물 주입을 용이하게 하여 접합 누설을 방지함으로써, 소자의 특성을 향상시키는 효과가 있다.As described above, according to the present invention, when forming a contact hole of a semiconductor device of 256M DRAM or higher, isotropic etching of a silicon substrate exposed in-situ after contact etching makes the silicon substrate having a field oxide film smoothed therein. Impurity can be easily injected into the silicon substrate having the field oxide film cut during the injection to prevent the junction leakage, thereby improving the characteristics of the device.
Claims (6)
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| KR1019960069248A KR100223774B1 (en) | 1996-12-20 | 1996-12-20 | Process for fabricating semicondcutor device with fine contact hole |
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