KR970013108A - Method of manufacturing a horizontal bipolar transistor - Google Patents

Method of manufacturing a horizontal bipolar transistor Download PDF

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Publication number
KR970013108A
KR970013108A KR1019950026165A KR19950026165A KR970013108A KR 970013108 A KR970013108 A KR 970013108A KR 1019950026165 A KR1019950026165 A KR 1019950026165A KR 19950026165 A KR19950026165 A KR 19950026165A KR 970013108 A KR970013108 A KR 970013108A
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KR
South Korea
Prior art keywords
polysilicon
forming
film
oxide
oxide film
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Application number
KR1019950026165A
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Korean (ko)
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KR0149317B1 (en
Inventor
박승진
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019950026165A priority Critical patent/KR0149317B1/en
Publication of KR970013108A publication Critical patent/KR970013108A/en
Application granted granted Critical
Publication of KR0149317B1 publication Critical patent/KR0149317B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6625—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors

Abstract

본 발명은 수평형 바이폴라 트랜지스터에 관한 것으로서, 질화규소 격벽의 폭을 미세화하여 슬롯의 폭을 조절하여 베이스 영역의 폭을 미세화하고, 베이스 영역의 이온 주입과 베이스 영역과 베이스 전극을 자기정합적으로 연결함으로써 특성 조절이 가능하게 되어 신뢰도를 향상시키는 수평형 바이폴라 트랜지스터의 제조 방법이다. 또한 베이스 전극과 폴리실리콘 격벽을 동시에 형성하여 공정이 간단하며, 베이스 전극과 격벽 형성시 습식 식각법을 이용함으로써, 실리콘 표면의 손상을 방지하여 양호한 소자를 제조할 수 있는 수평형 바이폴라 트랜지스터의 제조 방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal bipolar transistor, in which the width of a silicon nitride partition wall is adjusted to reduce the width of a slot, thereby minimizing the width of the base region. It is a method of manufacturing a horizontal bipolar transistor that can be adjusted to improve the reliability. In addition, the process is simple by simultaneously forming the base electrode and the polysilicon barrier ribs, and by using a wet etching method when forming the base electrode and the barrier ribs, a method of manufacturing a horizontal bipolar transistor capable of producing a good device by preventing damage to the silicon surface. to be.

Description

수평형 바이폴라 트랜지스터의 제조 방법Method of manufacturing a horizontal bipolar transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 (가) ∼ (바)는 본 발명에 의한 수평형 바이폴라 트랜지스터의 제조 방법을 그 공정 순서에 따라 도시한 단면도이다.2A to 2B are cross-sectional views illustrating a method for manufacturing a horizontal bipolar transistor according to the present invention, in accordance with the procedure thereof.

Claims (4)

제1 도전형 반도체 기판위에 제1 산화막과 제2 도전형 폴리실리콘막을 차례로 적응한 다음, 폴리실리콘막위에 절연막 패턴을 형성하는 제1 공정, 상기 절연막 패턴의 양 측면에 질화규소 격벽을 형성하고, 상기 절연막 패턴 한쪽의 상기한 질화규소 격벽을 제거하고, 상기 폴리실리콘막의 표면에 제2 산화막을 형성하는 제2 공정, 상기 절연막 패턴의 다른 한쪽의 상기 질화규소 격벽을 제거하여 아래의 상기 폴리실리콘막의 일부가 노출되도록 하고 노출된 폴리실리콘막을 식각하여 상기 제1 산화막의 일부가 노출되도록 하는 제3 공정, 상기 제1 산화막의 노출된 부분과 기판 표면의 상기 제2 산화막을 제거하여 슬롯을 형성하고, 상기 슬롯을 통하여 이온을 주입하여 베이스 영역을 형성하는 제4 공정, 상기 반도체 기판 전면에 폴리실리콘층을 적층한 다음 상기 폴리실리콘층과 그 아래에 형성되어 있는 상기 폴리실리콘막을 식각하여 베이스 전극을 형성하고, 동시에 베이스 전극의 양 측면에 폴리실리콘 격벽을 형성하는 제5 공정, 상기 산화막 패턴을 제거하고, 상기 베이스 전극의 측면에 산화규소 격벽을 형성한 다음 제1 도전형 불순물을 고농도로 이온 주입하여 에미터 영역과 콜렉터 영역을 형성하는 제6 공정을 포함하는 수평형 바이폴라 트랜지스터의 제조 방법.A first step of sequentially applying a first oxide film and a second conductive polysilicon film on a first conductive semiconductor substrate, and then forming an insulating film pattern on the polysilicon film; forming silicon nitride barrier ribs on both sides of the insulating film pattern, and A second step of removing the silicon nitride partition walls on one side of the insulating film pattern, forming a second oxide film on the surface of the polysilicon film, and removing the silicon nitride partition walls on the other side of the insulating film pattern to expose a portion of the polysilicon film below And etching the exposed polysilicon film to expose a portion of the first oxide film, removing the exposed portion of the first oxide film and the second oxide film on the substrate surface to form a slot, and removing the slot. In the fourth step of forming a base region by implanting ions through, a polysilicon layer is laminated on the entire surface of the semiconductor substrate A fifth step of forming a base electrode by etching the polysilicon layer and the polysilicon layer formed thereon, and simultaneously forming a polysilicon barrier rib on both sides of the base electrode, removing the oxide layer pattern, and removing the base electrode. And forming a emitter region and a collector region by forming silicon oxide barrier ribs on the side surfaces of the silicon oxide barrier ribs and ion implanting the first conductivity type impurities at a high concentration. 제1항에, 상기 질화규소 격벽은 상기 제1 산화막과 상기 절연막 패턴과 다른 식각률을 갖는 수평형 바이폴라 트랜지스터의 제조 방법.The method of claim 1, wherein the silicon nitride partition wall has an etching rate different from that of the first oxide layer and the insulating layer pattern. 제1항에, 상기 제4공정에서 상기 제1 산화막의 일부분과 기판 표면의 상기 제2 산화막을 습식 식각법으로 제거하는 수평형 바이폴라 트랜지스터의 제조 방법.The method of claim 1, wherein, in the fourth process, a portion of the first oxide film and the second oxide film on the surface of the substrate are removed by a wet etching method. 제1항에, 상기 폴리실리콘층과 상기 폴리실리콘막을 습식 식각의 방법으로 식각하여 베이스 전극과 폴리실리콘 격벽을 형성하는 수평형 바이폴라 트랜지스터의 제조 방법.The method of claim 1, wherein the polysilicon layer and the polysilicon layer are etched by a wet etching method to form a base electrode and a polysilicon barrier rib.
KR1019950026165A 1995-08-23 1995-08-23 Method of fabricating horizontal bipolar transistor KR0149317B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950026165A KR0149317B1 (en) 1995-08-23 1995-08-23 Method of fabricating horizontal bipolar transistor

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Application Number Priority Date Filing Date Title
KR1019950026165A KR0149317B1 (en) 1995-08-23 1995-08-23 Method of fabricating horizontal bipolar transistor

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KR970013108A true KR970013108A (en) 1997-03-29
KR0149317B1 KR0149317B1 (en) 1998-12-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030014062A (en) * 2001-08-10 2003-02-15 씨엘디 주식회사 Manufacturing Method of Partition Wall of Organic Electroluminescent Device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100661724B1 (en) * 2005-12-28 2006-12-26 동부일렉트로닉스 주식회사 Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030014062A (en) * 2001-08-10 2003-02-15 씨엘디 주식회사 Manufacturing Method of Partition Wall of Organic Electroluminescent Device

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