KR19980043412A - Contact wiring formation method of semiconductor device - Google Patents
Contact wiring formation method of semiconductor device Download PDFInfo
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- KR19980043412A KR19980043412A KR1019960061259A KR19960061259A KR19980043412A KR 19980043412 A KR19980043412 A KR 19980043412A KR 1019960061259 A KR1019960061259 A KR 1019960061259A KR 19960061259 A KR19960061259 A KR 19960061259A KR 19980043412 A KR19980043412 A KR 19980043412A
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title abstract description 14
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 20
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 15
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
반도체 소자의 콘택배선 형성방법에 대한 것으로 콘택배선이 형성되는 부분의 불순물 영역을 기판이 드러나도록 식각하고, 드러난 기판의 소정 영역에 산화막을 형성한 후에 배선 형성공정을 하여 기판과 졍션 부분의 기생 캐패시터를 줄이고 이에 따라 접합 누설 전류를 줄이고 또한 메모리 소자에서의 콘택배선을 통한 센싱 능력도 향상시킨다.A method of forming contact wiring of a semiconductor device, wherein the impurity region of the portion where the contact wiring is formed is etched so that the substrate is exposed, and an oxide film is formed in a predetermined region of the exposed substrate, and then a wiring forming process is performed to form a parasitic capacitor of the substrate and the junction portion. This reduces the leakage current and improves the sensing capability of the contact wiring in the memory device.
Description
본 발명은 콘택배선에 대한 것으로 특히 기생 캐패시터를 감소시키기에 적당한 콘택홀 공정을 이용한 반도체 소자의 콘택배선 형성방법에 대한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to contact wiring, and more particularly, to a method of forming contact wiring in a semiconductor device using a contact hole process suitable for reducing parasitic capacitors.
이하 첨부 도면을 참조하여 종래의 반도체 소자의 콘택배선 형성방법에 대하여 설명하면 다음과 같다.Hereinafter, a method for forming contact wiring of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a와 1b는 종래의 반도체 소자의 콘택배선 형성방법을 나타낸 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method for forming contact wiring in a conventional semiconductor device.
종래의 콘택배선 형성방법은 먼저 도 1a에 도시한 바와 같이 P형 기판(1)에 활성영역과 필드절연막(12)을 형성하고 전면에 산화막과 폴리 실리콘을 증착한 후 게이트 형성 마스크로 패터닝하여 게이트 산화막(3)과 게이트 전극(4)을 적층하여 형성한다. 이후에 드러난 P형 기판(1)에 n- 소오스/드레인 이온을 주입하여 저농도 소오스/드레인 영역(5)을 형성하고 전면에 산화막을 증착하여 이방성 식각으로 게이트 측벽 절연막(6)을 형성한다. 다음에 게이트 측벽 절연막(6)과 게이트 전극(4)을 마스크로 하여 P형 기판(1)에 n+ 소오스/드레인 이온을 주입하여 고농도 소오스/드레인 영역(7)을 형성한다. 그리고 전면에 산화막을 증착하고 게이트 전극(4) 사이의 소오스/드레인 영역이 드러나도록 콘택홀을 형성한다.In the conventional method of forming a contact wiring, first, as shown in FIG. 1A, an active region and a field insulating layer 12 are formed on a P-type substrate 1, an oxide layer and polysilicon are deposited on the entire surface, and then patterned with a gate forming mask. The oxide film 3 and the gate electrode 4 are laminated. Subsequently, n-source / drain ions are implanted into the exposed P-type substrate 1 to form a low concentration source / drain region 5, and an oxide film is deposited on the entire surface to form the gate sidewall insulating layer 6 by anisotropic etching. Next, n + source / drain ions are implanted into the P-type substrate 1 using the gate sidewall insulating film 6 and the gate electrode 4 as a mask to form a high concentration source / drain region 7. An oxide film is deposited on the entire surface, and contact holes are formed to expose source / drain regions between the gate electrodes 4.
도 1b에 도시한 바와 같이 전면에 n+ 폴리 실리콘을 증착하고 에치백하여 상기 콘택홀 내를 채우도록 n+ 폴리플러그(9)를 형성하고 전면에 폴리 실리콘이나 알루미늄 또는 텅스텐과 같은 전도성 물질을 증착하여 배선을 형성한다. 상기의 콘택홀에 n+ 폴리플러그(9)를 형성하면 P형 기판(1)과 n+ 이온을 주입하여 형성한 소오스/드레인 영역과 n+ 폴리플러그(9)가 접한 평면에 PN 콘택 졍션이 형성되고 이에 따라 접합 부분에 생기는 공핍층에 의해 기생 캐패시터가 형성되고 특히 디램에서는 비트 라인 콘택 졍션 캐패시터가 디램의 메모리 셀의 캐패시터에 비해 커서 접합 누설 전류가 발생된다.As shown in FIG. 1B, n + polysilicon is deposited on the front surface and etched back to form n + polyplug 9 to fill the contact hole, and a conductive material such as polysilicon, aluminum, or tungsten is deposited on the front surface. To form. When the n + polyplug 9 is formed in the contact hole, a PN contact junction is formed on a plane where the source / drain region formed by implanting the P-type substrate 1 and n + ions and the n + polyplug 9 are in contact with each other. As a result, parasitic capacitors are formed by the depletion layer formed at the junctions. In particular, in DRAM, the bit line contact capacitor is larger than the capacitor of the DRAM memory cell to generate a junction leakage current.
상기와 같이 제조되는 종래의 반도체 소자의 콘택배선 형성방법은 다음과 같은 문제점이 있다.The conventional method for forming contact wiring of a semiconductor device manufactured as described above has the following problems.
n+ 이온 주입된 영역과 P형 기판이 접하는 콘택 영역에 콘택 졍션이 발생되고 이 접합 부분에 생기는 공핍측에서 기생 캐패시터가 발생되어 졍션 누설 전류가 발생하므로 소자의 신뢰성이 떨어진다.A contact junction is generated in the contact region where the n + ion implanted region and the P-type substrate are in contact with each other, and a parasitic capacitor is generated at the depletion side generated at the junction, resulting in a leakage leakage current.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로써 기생 캐패시터를 감소시켜서 신뢰성 있는 반도체 소자의 콘택배선 형성방법을 제공하는 데 그 목적이 있다.An object of the present invention is to provide a method for forming a reliable contact wiring of a semiconductor device by reducing parasitic capacitors.
도 1a와 1b는 종래의 반도체 소자의 콘택배선 형성방법을 나타낸 공정 단면도1A and 1B are cross-sectional views illustrating a method of forming contact wirings in a conventional semiconductor device.
도 2a 내지 2d는 본 발명 반도체 소자의 콘택배선 형성방법을 나타낸 공정 단면도2A to 2D are cross-sectional views illustrating a method for forming contact wirings in a semiconductor device of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11 : P형 기판12 : 필드 절연막11: P-type substrate 12: Field insulating film
13 : 게이트 산화막14 : 게이트 전극13 gate oxide film 14 gate electrode
15 : 저농도 소오스/드레인 영역16 : 게이트 측벽 절연막15 low concentration source / drain region 16 gate sidewall insulating film
17 : 고농도 소오스/드레인 영역18 : 층간 절연막17 high concentration source / drain region 18 interlayer insulating film
19 : 질화막19a : 측벽 질화막19 nitride film 19a sidewall nitride film
20 : 산화막21 : n+ 폴리플러그20: oxide film 21: n + poly plug
22 : 배선층22: wiring layer
상기와 같은 목적을 달성하기 위한 본 발명 반도체 소자의 콘택배선 형성방법은 제 1 도전형 기판에 활성영역과 필드절연막을 형성하는 공정과, 상기 활성영역상에 게이트 산화막과 상기 게이트 산화막상에 게이트 전극을 형성하는 공정과, 상기 게이트 전극 양측의 기판에 제 2 도전형 불순물 영역 형성하는 공정과, 상기 전면에 층간 절연막을 형성하는 공정과, 상기 게이트 전극 일측의 상기 제 1 도전형 기판이 드러나도록 콘택홀을 형성하는 공정과, 상기 콘택홀 측면에 제 1 절연막을 형성하는 공정과, 상기 콘택홀 하부의 소정 영역에 제 2 절연막을 형성하는 공정과, 상기 제 1 절연막을 제거하는 공정과, 상기 콘택홀의 상기 불순물 영역과 콘택되도록 제 2 도전형 플러그층을 형성하는 공정을 포함함을 특징으로 한다.The method for forming a contact wiring of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an active region and a field insulating film on a first conductivity type substrate, a gate oxide film on the active region, and a gate electrode on the gate oxide film. Forming a second conductive impurity region on the substrates on both sides of the gate electrode, forming an interlayer insulating film on the front surface, and exposing the first conductive substrate on one side of the gate electrode. Forming a hole, forming a first insulating film on the side of the contact hole, forming a second insulating film in a predetermined region under the contact hole, removing the first insulating film, and And forming a second conductive plug layer to be in contact with the impurity region of the hole.
이하 첨부 도면을 참조하여 본 발명 반도체 소자의 콘택배선 형성방법을 설명하면 다음과 같다.Hereinafter, a method for forming contact wiring of a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 2d는 본 발명 반도체 소자의 콘택배선 형성방법을 나타낸 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method for forming contact wiring in a semiconductor device of the present invention.
본 발명 반도체 소자의 콘택배선 형성방법은 먼저 도 2a에 도시한 바와 같이 P형 기판(11)에 활성영역과 필드절연막(12)을 형성하고 전면에 산화막과 폴리 실리콘을 증착한 후 게이트 형성 마스크로 패터닝하여 복수개의 게이트 산화막(13)과 게이트 전극(14)을 적층하여 형성한다. 이후에 드러난 P형 기판(11)에 n- 소오스/드레인 이온을 주입하여 저농도 소오스/드레인 영역(15)을 형성하고 전면에 산화막이나 질화막을 증착하여 이방성 식각으로 게이트 측벽 절연막(16)을 형성한다. 다음에 게이트 측벽 절연막(16)과 게이트 전극(14)을 마스크로 하여 P형 기판(11)에 n+ 소오스/드레인 이온을 주입하여 고농도 소오스/드레인 영역(17)을 형성한다. 그리고 전면에 산화막을 증착하고 패터닝하여 층간 절연막(18)을 형성한다. 그리고 상기 게이트 전극(14) 사이의 상기 층간 절연막(18)과 고농도 소오스/드레인 영역(17) 및 P형 기판(11)을 적절한 깊이까지 과도 식각하여 P형 기판(11)이 드러나도록 콘택홀을 형성한다.In the method of forming a contact wiring of a semiconductor device according to the present invention, as shown in FIG. 2A, an active region and a field insulating film 12 are formed on a P-type substrate 11, an oxide film and polysilicon are deposited on the entire surface, and then a gate forming mask. Patterning is performed by stacking a plurality of gate oxide films 13 and gate electrodes 14. Subsequently, n-source / drain ions are implanted into the exposed P-type substrate 11 to form a low concentration source / drain region 15, and an oxide or nitride film is deposited on the entire surface to form the gate sidewall insulating layer 16 by anisotropic etching. . Next, n + source / drain ions are implanted into the P-type substrate 11 using the gate sidewall insulating film 16 and the gate electrode 14 as a mask to form a high concentration source / drain region 17. An oxide film is deposited on the entire surface and patterned to form an interlayer insulating film 18. Then, the contact hole is exposed so that the P-type substrate 11 is exposed by over-etching the interlayer insulating layer 18, the high concentration source / drain region 17, and the P-type substrate 11 between the gate electrode 14 to an appropriate depth. Form.
도 2b에 도시한 바와 같이 전면에 화학 기상 증착법(CVD)으로 200~300Å 정도의 두께를 갖도록 질화막(19)을 증착한다.As illustrated in FIG. 2B, a nitride film 19 is deposited on the entire surface thereof to have a thickness of about 200 to 300 kPa by chemical vapor deposition (CVD).
도 2c에 도시한 바와 같이 이방성 식각으로 상기 질화막(19)을 식각하여 상기 콘택홀 측면 측벽 질화막(19a)을 형성한 다음에 열산화 공정을 통하여 드러난 P형 기판(11)에 산화막(20)을 형성한다.As shown in FIG. 2C, the nitride layer 19 is etched by anisotropic etching to form the contact hole sidewall nitride layer 19a, and then the oxide layer 20 is formed on the P-type substrate 11 exposed through the thermal oxidation process. Form.
도 2d에 도시한 바와 같이 등방성 식각으로 상기 측벽 질화막(19a)을 제거한 후 전면에 n+ 폴리실리콘을 증착하고 에치백하여 콘택홀 내에 n+ 폴리플러그(12)를 형성한다. 그리고 폴리 실리콘이나 알루미늄 또는 텅스텐과 같은 전도성 물질을 증착하여 배선층(22)을 형성한다. 여기에서 상기의 산화막을 PN 정션의 콘택배선 영역에 형성하므로써 종래의 기생 캐패시터 대신 산화막에 의한 순수한 산화막 캐패시터를 형성하므로 PN 정션에 의한 공핍층을 차단할 수 있으므로 기생 캐패시터를 감소시킬 수 있고 이에 따라 접합부분으로 전류가 누설되는 것을 방지할 수 있다. 특히 디램에서는 이와 같은 콘택배선을 통하여 CB/CS(기판의 캐패시터/소오스의 캐패시터)의 비율을 감소시키고 센싱 능력을 향상시킬 수 있으며 또한 고집적 소자의 콘택배선 형성에 적용할 수 있다.As shown in FIG. 2D, the sidewall nitride layer 19a is removed by isotropic etching, and then n + polysilicon is deposited on the entire surface and etched back to form n + polyplug 12 in the contact hole. Then, the wiring layer 22 is formed by depositing a conductive material such as polysilicon, aluminum, or tungsten. Here, by forming the oxide film in the contact wiring region of the PN junction, a pure oxide film capacitor is formed by the oxide film instead of the conventional parasitic capacitor, so that the depletion layer by the PN junction can be blocked, thereby reducing the parasitic capacitor and thus the junction portion. This can prevent leakage of current. In particular, DRAM can reduce the ratio of C B / C S (capacitor on substrate / capacitor on source), improve sensing capability, and can be applied to contact wiring formation of highly integrated devices.
상기와 같이 형성되는 본 발명 반도체 소자의 콘택배선 형성방법은 다음과 같은 효과가 있다.The contact wiring forming method of the semiconductor device of the present invention formed as described above has the following effects.
첫째, PN 정션이 형성되는 부분의 소정 영역에 산화막을 형성하므로써 이 부분에서의 공핍층 형성을 차단할 수 있고 이에 따라 기생 캐패시터를 감소시킬 수 있으며 또한 정션부분으로 전류가 누설되는 것을 방지할 수 있다.First, by forming an oxide film in a predetermined region of the portion where the PN junction is formed, it is possible to block the depletion layer formation at this portion, thereby reducing the parasitic capacitor and preventing leakage of current to the junction portion.
둘째, 디램에서는 CB/CS(기판의 캐패시터/소오스의 캐패시터)의 비율을 감소시켜서 센싱 능력을 향상시킬 수 있고 또한 고집적 소자의 콘택배선 형성에도 적용할 수 있다.Second, in DRAM, the sensing ratio can be improved by reducing the ratio of C B / C S (capacitor on substrate / capacitor on source), and can also be applied to contact wiring formation of highly integrated devices.
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| KR100685578B1 (en) * | 2005-04-26 | 2007-02-22 | 주식회사 하이닉스반도체 | Semiconductor device |
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