KR20000043223A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to form a uniform thickness of a screen thin film by using an etch barrier. CONSTITUTION: A method for manufacturing a semiconductor device comprises the following steps. An accumulating structure of a gate insulating layer(14) and a gate electrode(16a) is formed on an upper portion of a wafer(12) with a chip area(I) and an EM box(II). A screen thin film(18) and an etch barrier are formed on the upper portion of the wafer. The etching barrier and an insulating layer having an etch selectivity are formed on an upper portion of the etch barrier. An insulating layer spacer(22) is formed at a side wall of the accumulating structure by etching the insulating layer. A thickness of the screen thin film is formed uniformly by etching the etch barrier.

Description

Manufacturing method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a screen layer is formed to prevent wafer damage by an implant process for forming a source / drain junction region in a MOS FET. The present invention relates to a technique of uniformly forming a thickness of the screen thin film by using a nitride film as an etch stop layer during the process.

As the semiconductor device is highly integrated, the width of the gate electrode of the MOS FET is also decreased. However, when the width of the gate electrode is reduced by N times, the electrical resistance of the gate electrode is increased by N times, thereby reducing the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, polyside, which is a laminated structure of the polysilicon layer and the silicide, is used as the low resistance gate electrode by using the property of the polysilicon layer / oxide film interface exhibiting the most stable MOS FET characteristics.

In general, the most important function of the transistor constituting the semiconductor circuit is the current driving capability, and the channel width of the MOS FET is adjusted in consideration of this. The most widely used MOS FET uses a polysilicon layer doped with an impurity as a gate electrode, and a source / drain junction region uses a dopant-doped diffusion region on a wafer. Here, the sheet resistance of the gate electrode is about 30 to 70 Ω / □, the sheet resistance of the source / drain junction region is about 70 to 150 Ω / □ for N + and 100 to 250 Ω / □ for P +, and the gate electrode or source / drain In the case of a contact formed on the junction region, the contact resistance is 30 to 70? /? Per contact.

As described above, in order to reduce high sheet resistance and contact resistance of the gate electrode and the source / drain junction region, increase the operation speed of the device, and lower the topology by the gate electrode, a salicide (self-aligned silicide) method or selective method is used. A metal silicide film was formed only on the gate electrode and the source / drain junction region by the metal film deposition method to increase the current driving capability of the MOS FET. When Ti silicide is used in the silicide layer, the sheet resistance of the gate electrode and the source / drain junction region is reduced to about 5 Ω / □ and the contact resistance is about 30 Ω / □ or less per contact, resulting in a current driving capability of MOS FET of 40% or more. This allows for higher integration of the MOS FETs.

In general, a PN junction formed of an N-type or P-type impurity on a P-type or N-type wafer is ion implanted into the wafer and then activated by heat treatment to form a diffusion region. Therefore, in a semiconductor device having a reduced channel width, a screen oxide layer is formed to form a shallow junction depth in order to prevent short channel effects due to side diffusion from the diffusion region.

Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in an EM box and a chip region on a wafer according to the prior art.

First, a desired type of impurity is implanted into a desired portion of the wafer 11 having the chip region I and the EM box region II to form a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region. After the impurities are present, a device isolation insulating film (not shown) is formed on the portion of the wafer, which is intended as a device isolation region.

Next, a gate insulating layer 13 is formed over the entire surfaces of the chip region I and the EM box region II, and a conductive layer 15 for the gate electrode is formed over the gate insulating layer 13.

Next, the gate electrode conductive layer 15 and the gate insulating layer 13 having a predetermined thickness are etched on the chip region I by using a gate electrode mask (not shown) to form the gate electrode 15a and the gate insulating layer pattern. The laminated structure of (13a) is formed.

Next, low concentration impurities are ion-implanted into both wafers 11 of the stacked structure to form a lightly doped drain (LDD) region.

Then, an insulating film (not shown) is deposited on the chip region I and the EM box region II, and then the insulating layer on the chip region I is etched to the entire surface to form an insulating film spacer 17 on the sidewall of the stacked structure. ). At this time, a residual insulating film 19 having a predetermined thickness remains on the wafer 11. In this case, the residual insulating film 19 is used as a screen thin film as the gate insulating film 13 having a predetermined thickness remaining during the etching process for forming the gate electrode.

Thereafter, a high concentration of impurities are implanted into the wafer 11 through the residual insulating film 19 to form a source / drain junction region (not shown). (See Fig. 1)

As described above, in the method of manufacturing a semiconductor device according to the related art, since a short channel effect occurs in a MOS field effect transistor as the semiconductor device becomes highly integrated, a low junction is formed when forming a source / drain junction region of the MOS field effect transistor. Or a screen thin film is formed on the wafer at the portion where the source / drain junction region is formed to form an LDD structure. However, the screen thin film is formed thin at the center of the wafer and thick at the edge due to the difference in deposition and etching rates depending on the position on the wafer or the pattern of the underlying layer. In order to solve the above problems, the monitoring method in the EM box is corrected or the uniformity of the values measured in the EM box is improved, but the chip area and the pattern formed in the EM box are not equal to each other. Even in the region, the thickness of the screen thin film between the cell region and the peripheral circuit region was not uniform. As described above, if the screen thin film is formed thick at the edge of the wafer, the depth of the source / drain junction region is made small, resulting in severe damage to the junction region during the subsequent contact process, resulting in leakage current, resulting in poor process yield and device operation reliability. There is a problem.

In order to solve the above problems of the prior art, the gate electrode is formed, the screen thin film and the nitride film are sequentially formed, and then an insulating film having an etching selectivity with the nitride film is formed on the nitride film. An insulating film spacer is formed on the sidewall of the gate electrode by using a nitride film as an etch stop layer, and then the nitride film is removed to uniformly form the thickness of the screen thin film in the chip region and the EM box. It is an object of the present invention to provide a method for manufacturing a semiconductor device that improves the efficiency.

1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device in an EM box and a chip region on a wafer according to the prior art;

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in an EM box and a chip region on a wafer in accordance with the present invention.

<Description of Symbols for Major Parts of Drawings>

11, 12: wafer 13, 14: gate insulating film

13a and 14a: Gate insulating film patterns 15 and 16: Conductive layer for gate electrode

15a, 16a gate electrode 17, 22: insulating film spacer

18: screen oxide film 19: residual oxide film

20: etching prevention film

Ⅰ: Chip area Ⅱ: EM box area

Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

Forming a stacked structure of a gate insulating film and a gate electrode on an upper surface of the wafer provided with a chip region and an EM box;

Sequentially forming a screen thin film and an etch stop layer on the wafer;

Forming an insulating film having an etch selectivity with the etch stop layer on the etch stop layer;

Forming an insulating film spacer on the sidewall of the stacked structure by etching the entire insulating film;

And removing the entire surface etching process of the etch stop layer to uniformly form a thickness of the screen thin film.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in an EM box and a chip region on a wafer according to the present invention.

First, a desired type of impurity is implanted into a desired portion of the wafer 12 having the chip region I and the EM box region II, thereby forming a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region. After the impurities are present, a device isolation insulating film (not shown) is formed on the portion of the wafer 12, which is intended as a device isolation region.

Next, the gate insulating layer 14 and the gate electrode conductive layer 16 are formed over the entire surface, and the gate electrode 16a is etched by using a gate electrode mask in a portion of the chip region I, which is intended as the gate electrode. ) And the gate insulating film pattern 14a are formed. At this time, the gate insulating layer 14 is left on the wafer 12 to prevent damage to the wafer 12 during the subsequent ion implantation process.

Next, low concentration impurities are ion implanted on both wafers 12 of the stacked structure to form an LDD region (not shown). (See Figure 2A)

Next, the screen thin film 18 is formed of an oxide film on the entire surface, and the etch stop layer 20 is formed of a nitride film on the screen thin film 18. (See FIG. 2B, FIG. 2C)

Next, an insulating film (not shown) is formed on the etch stop layer 20, and then the entire surface is etched to form an insulating film spacer 22 on the sidewall of the gate electrode. All of the insulating films on the EM box region II are removed. (See FIG. 2D)

Next, the etch stop layer 20 is removed by full etching. In this case, the screen thin film 18 is uniformly formed on the chip region I and the EM box region II. (See Figure 2E)

Thereafter, a high concentration of impurities are ion implanted into the wafer 12 through the screen thin film 18 to form a source / drain junction region (not shown).

As described above, in the method of manufacturing a semiconductor device according to the present invention, a gate electrode is formed on a wafer having a chip region and an EM box region, a screen thin film and a nitride film are sequentially formed, and then the upper portion of the nitride film is formed. After forming an insulating film having an etch selectivity with a nitride film, an insulating film spacer is formed on the sidewall of the gate electrode by the front etching process using the nitride film as an etch stop layer, and the nitride film is removed to remove the nitride film. The thickness of the screen thin film is uniformly formed to easily form a low junction during the subsequent ion implantation process, to secure a process margin during the contact process, to reduce the junction leakage current in the junction region, and to uniformly implant the ion There is an advantage to improve the characteristics and thereby high integration of the semiconductor device.

Claims (3)

Forming a stacked structure of a gate insulating film and a gate electrode on an upper surface of the wafer provided with a chip region and an EM box; Sequentially forming a screen thin film and an etch stop layer on the wafer; Forming an insulating film having an etch selectivity with the etch stop layer on the etch stop layer; Forming an insulating film spacer on the sidewall of the stacked structure by etching the entire insulating film; And removing the entire surface etching process of the etch stop layer to uniformly form a thickness of the screen thin film. The method of claim 1, The screen thin film is a method of manufacturing a semiconductor device, characterized in that the oxide film. The method of claim 1, The etching prevention film is a semiconductor device manufacturing method, characterized in that the nitride film.