KR100284133B1 - Self-aligned contact formation method of semiconductor device - Google Patents

Self-aligned contact formation method of semiconductor device Download PDF

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Publication number
KR100284133B1
KR100284133B1 KR1019940018407A KR19940018407A KR100284133B1 KR 100284133 B1 KR100284133 B1 KR 100284133B1 KR 1019940018407 A KR1019940018407 A KR 1019940018407A KR 19940018407 A KR19940018407 A KR 19940018407A KR 100284133 B1 KR100284133 B1 KR 100284133B1
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South Korea
Prior art keywords
etching
self
semiconductor device
aligned contact
oxide film
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KR1019940018407A
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Korean (ko)
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KR960005799A (en
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이석희
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

Abstract

본 발명은 반도체 소자의 자기정렬 콘택 형성 방법에 관한 것으로, 소자의 크기가 극소화 됨에 따라 사진(Photo)공정에서의 정렬오차(Misalign)등으로 인한 소자의 신뢰성 저하를 방지하기위해 산화막과의 식차 선택비가 크고 절연성이 우수한 SIPOS층을 식각 장벽(Etch Barrier)으로 사용하므로써 소자의 전기적 특성을 안정화시키고 접촉면적의 충분한 확보로 소자의 신뢰성을 향상시킬수 있도록 한 반도체 소자의 자기정렬 콘택형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a self-aligned contact of a semiconductor device. As the size of the device is minimized, a formula difference with an oxide film is selected in order to prevent a decrease in reliability of the device due to misalignment in a photo process. The present invention relates to a method for forming a self-aligned contact of a semiconductor device in which a non-conventional and excellent insulating SIPOS layer is used as an etching barrier to stabilize the electrical characteristics of the device and to improve the reliability of the device by securing sufficient contact area.

Description

반도체 소자의 자기정렬 콘택 형성방법Self-aligned contact formation method of semiconductor device

제1(a)도 내지 제1(d)도는 본 발명에 따른 반도체 소자의 자기정렬 콘택 형성 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of a device for explaining a method of forming a self-aligned contact of a semiconductor device according to the present invention.

제2도는 정렬오차가 심하게 발생된 콘택홀의 단면도.2 is a cross-sectional view of a contact hole in which an alignment error is severely generated.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film

3 : 게이트 산화막 4 : 폴리 실리콘층3: gate oxide film 4: polysilicon layer

4A : 워드라인 또는 게이트전극 6 : 불순물 영역4A: word line or gate electrode 6: impurity region

7 : 산화막 스페이서 8 : 질화막7 oxide film spacer 8 nitride film

9 : SIPOS층 10 : BPSG9: SIPOS layer 10: BPSG

11 : 감광막 12 : 콘택홀11: photosensitive film 12: contact hole

본 발명은 반도체 소자의 자기정렬 콘택(Self-align contact)형성방법에 관한 것으로, 특히 산화막(Oxide)과의 식각 선택비가 크고 절연성이 우수한 SIPOS(Semi-Insulating-Polycrystalline Silicon)층을 식각 장벽(Etch Barrier)으로 사용하므로써 소자의 신뢰성을 향상시킬수 있는 반도체 소자의 자기정렬 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a self-aligned contact of a semiconductor device. In particular, a semi-insulating-polycrystalline silicon (SIPOS) layer having a high etching selectivity with respect to oxide and excellent insulation is etched. The present invention relates to a method for forming a self-aligned contact of a semiconductor device, which can be used as a barrier.

종래 DRAM 및 SRAM과 같은 고집적화된 반도체 소자의 콘택 홀(Contact hole)형성에 있어, 소자의 크기가 극소화 됨에 따라 사진(photo) 공정에서의 정렬오차(Misalign)등으로 인한 폴리 층(Poly Layer)과 폴리층의 접촉(Short)으로 소자의 신뢰성이 크게 저하된다. 이와같은 문제점을 해결하기 위해 스페이서 (Spacer)를 이용한 자기정렬 콘택 형성 방법을 이용하지만 공정이 복잡하고 정렬오차에 의한 문제점이 완전히 해결되지않으며 충분한 접촉(Contact)면적의 확보가 어렵다.In the formation of contact holes in highly integrated semiconductor devices such as DRAM and SRAM, as the size of the device is minimized, the poly layer due to misalignment in the photo process and the like The contact of the poly layer (Short) greatly reduces the reliability of the device. In order to solve such a problem, a self-aligned contact forming method using a spacer is used, but the process is complicated, the problem due to the alignment error is not completely solved, and sufficient contact area is difficult to secure.

따라서 본 발명은 산화막(Oxide)과의 식각 선택비 가 크고 절연성이 우수한 SIPOS층을 식각 장벽으로 사용하므로써 상기한 단점을 해소할수 있는 반도체 소자의 자기정렬 콘택 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a self-aligned contact of a semiconductor device, which can solve the above-mentioned disadvantages by using a SIPOS layer having a high etching selectivity with an oxide and excellent insulation as an etching barrier.

상기한 목적을 달성하기 위한 본 발명은 필드 산화막(2)이 형성된 실리콘 기판(1)상에 게이트 산화막(3), 폴리 실리콘층(4) 및 산화막(5)을 순차적으로 형성 한후 사진 및 식각공정에 의해 워드라인 또는 게이트 전극(4A)을 형성한 다음 상기 워드라인 또는 게이트 전극(4A)측벽에 산화막 스페이서(7)를 형성하고 전체 상부면에 질화막(8)을 소정두께로 형성시키는 단계와, 상기 단계로부터 SIPOS층(9) 및 BPSG(10)를 순차적으로 중착한후 상기 BPSG(10)를 플로우시키고 감광막(11)을 도포한 다음 패터닝시키는 단계와, 상기 단계로부터 상기 SIPOS층(9)을 식각장벽으로하여 상기 BPSG(10)를 식각한후 상기 SIPOS층(9)을 식각하는 단계와, 상기 단계로부터 산화막과의 식각선택비 차이를 이용하여 상기 질화막(8)을 식각한후 감광막(11)을 제거시키는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention sequentially forms a gate oxide film 3, a polysilicon layer 4, and an oxide film 5 on a silicon substrate 1 on which a field oxide film 2 is formed. Forming a word line or gate electrode 4A by forming an oxide spacer 7 on the sidewalls of the word line or gate electrode 4A and forming a nitride film 8 on the entire upper surface thereof to a predetermined thickness; Sequentially depositing the SIPOS layer 9 and the BPSG 10 from the step, and then flowing the BPSG 10 and applying and patterning the photoresist film 11; After etching the BPSG 10 as an etch barrier, the SIPOS layer 9 is etched, and the nitride film 8 is etched using the difference in etching selectivity with the oxide film from the step. Removing the step) It shall be.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제1(a)도 내지 제1(d)도는 본 발명에 따른 반도체 소자의 자기정렬 콘택 형성방법을 설명하기 위한 소자의 단면도로서, 제2도를 참조하여 설명하면 다음과 같다.1 (a) to 1 (d) are cross-sectional views of a device for explaining a method of forming a self-aligned contact of a semiconductor device according to the present invention. Referring to FIG.

제1(a)도는 필드산화막(2)이 형성된 실리콘 기판(1)상에 게이트 산화막(3), 폴리실리콘층(4) 및 산화막(5)을 순차적으로 형성한후 사진 및 식각공정에 의해 워드라인 또는 게이트 전극(4A)을 패터닝하고 전체 상부에 불순물 이온을 주입하여 불순물영역(6)을 형성한 다음 상기 워드라인 또는 게이트 전극(4A)측벽에 산화막 스페이서(7)를 형성하고 전체 상부면에 질화막(8)을 소정두께로 형성시킨 상태의 단면도이다.In FIG. 1 (a), the gate oxide film 3, the polysilicon layer 4, and the oxide film 5 are sequentially formed on the silicon substrate 1 on which the field oxide film 2 is formed, and then the words are photographed and etched. The impurity region 6 is formed by patterning the line or gate electrode 4A and implanting impurity ions into the entire upper portion, and then forming oxide film spacers 7 on the sidewalls of the word line or gate electrode 4A. It is sectional drawing in the state which formed the nitride film 8 to predetermined thickness.

제1(b)도는 600 내지 800℃의 온도에서 SiH4및 N2O 가스를 이용하여 SIPOS(9)을 소정두께로 증착한후 BPSG(10)를 중착하고 플로우(Flow)시 킨 다음 감광막(11)을 도포하고 패터닝한 상태의 단면도로서, 상기 SIPOS(9)내의 산소농도는 상기 N2O/ SiH4가스비를 조절하여 50 내지 60%가 되도록 한다.FIG. 1 (b) shows the deposition of SIPOS 9 to a predetermined thickness using SiH 4 and N 2 O gas at a temperature of 600 to 800 ° C., followed by depositing and flowing the BPSG 10, followed by photoresist ( 11) is a cross-sectional view of the coated and patterned state, the oxygen concentration in the SIPOS (9) is adjusted to 50 to 60% by adjusting the N 2 O / SiH 4 gas ratio.

제1(c)도는 산화막 식각장비내에서 상기 SIPOS층(9)을 식각장벽으로 하여 상기 BPSG층(10)을 식각한후, 폴리 실리콘 식각장비내에서 상기 SIPOS층(9)을 식각한 상태의 단면도로서, 산소 함유량이 50 내지 60%인 SIPOS층(9)은 산화막과의 식각선택비가 10 : 1 정도 되기때문에 BPSG(10) 식각시 식각장벽역할을 하며, 상기 폴리 실리콘 식각장비내에서는 SIPOS의 식각속도가 폴리 실리콘의 약 ¼ 정도 된다.In FIG. 1 (c), the BPSG layer 10 is etched using the SIPOS layer 9 as an etch barrier in the oxide etching apparatus, and the SIPOS layer 9 is etched in the polysilicon etching apparatus. As a cross-sectional view, the SIPOS layer 9 having an oxygen content of 50 to 60% acts as an etch barrier when etching BPSG 10 because the etching selectivity with the oxide film is about 10: 1, and in the polysilicon etching equipment, The etching rate is about 1/4 of polysilicon.

제1(d)도는 상기 질화막(8) 및 상기 감광막(11)을 순차적으로 제거하여 상기 불순물영역(6)이 노출되도록 콘택홀(12)을 형성시킨 상태의 단면도로서, 상기 질화막(8)식각시 하부의 게이트 산화막(3)과의 식각선택비는 10: 1 정도로 산화막 스페이서(7)는 거의 식각되지 않는다. 또한 상기 SIPOS(9)는 산소 함유량이 50 내지 60%일때 비저항이 1012내지 1014Ω·cm 정도로 언도프 폴리 실리콘의 106Ω·cm와 비교하여 절연성이 매우 크므로 콘택홀 형성후 제거할 필요가 없다. 만일 상기 의 사진 작업시 정렬오차가 심하게 발생되어 제2도와 같이 콘택홀(12)이 형성된 경우에도 산화막(5 및 7)에 의해 워드라인 또는 게이트 전극(4A)의 노출이 방지되어 소자의 전기적 특성이 안정화된다.1 (d) is a cross-sectional view of the contact hole 12 formed to sequentially expose the impurity region 6 by sequentially removing the nitride film 8 and the photosensitive film 11, and etching the nitride film 8 The oxide spacer 7 is hardly etched at an etching selectivity of 10 to 1 with the gate oxide film 3 at the bottom of the region. In addition, when the oxygen content is 50 to 60%, the SIPOS (9) has a specific resistance of about 10 12 to 10 14 Ω · cm, which is very high in insulation compared to 10 6 Ω · cm of undoped polysilicon, and thus can be removed after contact hole formation. no need. If the photo misalignment is severely generated and the contact hole 12 is formed as shown in FIG. Is stabilized.

상술한 바와같이 본 발명에 의하면 산화막과의 식각 선택비가 크고 절연성 이 우수한 SIPOS층을 식각 장벽으로 사용하므로써 소자의 전기적 특성을 안정화 시킬수 있고 접속면적이 충분히 확보되어 소자의 신뢰성을 향상시킬수 있는 탁월한 효과가 있다.As described above, according to the present invention, by using a SIPOS layer having a high etching selectivity with respect to an oxide film and having excellent insulation as an etching barrier, it is possible to stabilize the electrical characteristics of the device and to secure a sufficient connection area, thereby improving the reliability of the device. have.

Claims (3)

반도체 소자의 자기정렬 콘택 형성 방법에 있어서, 필드 산화막(2)이 형성된 실리콘 기판(1)상에 게이트 산화막(3), 폴리 실리콘층(4) 및 산화막(5)을 순차적으로 형성한후 사진 및 식각공정에 의해 워드라인 또는 게이트 전극(4A)을 형성한 다음 상기 워드라인 또는 게이트 전극(4A)측벽에 산화막 스페이서(7)를 형성하고 전체 상부면에 질화막(8)을 소정두께로 형성시키는 단계와, 상기 단계로부터 SIPOS층(9) 및 BPSG(10)를 순차적으로 증착한후 상기 BPSG(10)를 플로우 시키고 감광막(11)을 도포한 다음 패터닝 시키는 단계와, 상기 단계로부터 상기 SIPOS층(9)을 식각장벽으로하여 상기 BPSG(10)를 식각한후 상기 SIPOS층(9)을 식각하는 단계와, 상기 단계로부터 산화막과의 식각선택비 차이를 이용하여 상기 질화막(8)을 식각한후 감광막(11)을 제거시키는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 자기정렬 콘택 형성 방법.In the method for forming a self-aligned contact of a semiconductor device, the gate oxide film 3, the polysilicon layer 4 and the oxide film 5 are sequentially formed on the silicon substrate 1 on which the field oxide film 2 is formed, and then photographs and After the word line or gate electrode 4A is formed by an etching process, an oxide spacer 7 is formed on the sidewalls of the word line or gate electrode 4A, and the nitride film 8 is formed to a predetermined thickness on the entire upper surface. And sequentially depositing the SIPOS layer 9 and the BPSG 10 from the step, and then flowing the BPSG 10 and applying and patterning the photoresist film 11 therefrom. Etching the BPSG (10) using an etch barrier) and etching the SIPOS layer (9), and etching the nitride film (8) using the difference in etching selectivity with the oxide film from the step. (11) removing the step A method of forming a self-aligned contact of a semiconductor device, characterized in that. 제1항에 있어서, 상기 SIPOS층(9)은 600 내지 800℃의 온도에서 SiH4및 N2O 가스에 의해 형성되며, 내부의 산소농도는 상기 SiH4및 N2O 가스비의 조절에 의해 50 내지 60%인 것을 특징으로 하는 반도체 소자의 자기정렬 콘택 형성 방법.The method of claim 1, wherein the SIPOS layer (9) is formed by SiH 4 and N 2 O gas at a temperature of 600 to 800 ℃, the internal oxygen concentration is 50 by controlling the SiH 4 and N 2 O gas ratio Self-aligned contact forming method for a semiconductor device, characterized in that from 60% to 60%. 제1항에 있어서, 상기 BPSG층(10)의 식각은 산화막 식각장비 내에서 이루어지며 상기 SIPOS층(9)의 식각은 폴리 실리콘 식각장비내에서 이루어지는 것을 특징으로 하는 반도체 소자의 자기정렬 콘택 형성 방법.The method of claim 1, wherein the etching of the BPSG layer 10 is performed in an oxide etching apparatus and the etching of the SIPOS layer 9 is performed in a polysilicon etching apparatus. .
KR1019940018407A 1994-07-28 1994-07-28 Self-aligned contact formation method of semiconductor device KR100284133B1 (en)

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