JP2679668B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to element isolation formation and salicide process.

[0002]

2. Description of the Related Art Conventionally, for element isolation, a method has been generally used in which a field oxide film is formed in an isolation region (field region) by performing local thermal oxidation in a state where the element region is masked with a silicon nitride film. ing. Insulated gate field effect transistors (hereinafter MOSFE) using this method
(Referred to as T) is illustrated in FIG. In the same figure, the field oxide film 33 partially buried in the main surface 31S of the P-type silicon substrate 31 is formed by the above-mentioned method, and a polysilicon gate is formed in the device region partitioned by the gate insulating film 36. An electrode 37 is formed, a side wall oxide film 38 is formed on the side surface thereof, an N-type source / drain diffusion layer 34 is formed between the gate electrode 37 and the field oxide film 33, and an N-type source / drain region 34 and A refractory metal silicide layer 35, 35 is formed on the exposed upper surface of the polysilicon gate electrode 37 by a salicide process.
Are formed respectively.

However, in the above method, since the field silicon oxide film 33 enters below the silicon nitride film serving as a mask, so-called bird's beaks 33A are generated to make the boundary between the isolation region and the element region ambiguous, and in this state. When the silicide layer 35 is formed by
The stress causes the silicide layer 35 to become thinner at the edge of 4. For this reason, it has been attempted to reduce the bird's beak by forming a locally oxidized isolation region on a substrate portion dug in advance, but the above problem cannot be completely eliminated.

On the other hand, as the element isolation method, in addition to the above local oxidation method, a trench element isolation method has been developed in order to cope with the miniaturization of elements. In this method, a trench having a required isolation width is formed in advance in the substrate, and a silicon oxide film is embedded in the trench. Therefore, the ambiguity of the isolation region width caused by the thermal oxidation method as described above, that is, the isolation region and the element region There is no ambiguity in the boundaries between the elements, and the dimensions between the elements can be controlled to predetermined values. Regarding this element isolation method, for example, Japanese Patent Laid-Open No. 3-79033 discloses a technique as shown in FIG. In the same figure, a gate insulating film 46 is provided in an element region partitioned by a trench isolation region 43 formed by filling a silicon oxide film in a trench formed inside the main surface 41S of the P-type silicon substrate 41. To form a polysilicon gate electrode 47, and a side wall oxide film 48 is formed on the side surface thereof.
An N-type source / drain diffusion layer 44 is formed between the gate electrode 47 and the trench isolation region 43. The trench isolation region 43 is provided with flange portions 43A (FIG. 4A) and 43B (FIG. 4B) made of a silicon oxide film, and exposed between the flange portions 43A and 43B and the sidewall oxide film 48. A refractory metal silicide layer 45 is formed on the upper surfaces of the N-type source / drain regions 44 and the polysilicon gate electrode 47 by a salicide process.

[0005]

As described above, it is basically impossible to completely remove bird's beaks by the local oxidation method, however the method is improved. Therefore, as shown in FIG. The end portion of the silicide layer 35 that abuts the tip of the protruding bird's beak 33A is formed in a thin film shape. As a result, the silicide resistance of the diffusion layer 34 suddenly increases as the line width (width of the diffusion layer) becomes smaller. Moreover, when the element is miniaturized and the width of the isolation region is narrowed, that is, the field silicon oxide film 3 between the element regions is reduced.
When the lateral dimension of 3 becomes small, the silicide layer which has grown up from the diffusion layer 34 at both ends of the isolation region 33 to the isolation region of the tapered bird's beak does not ensure the isolation, and the leakage current between the elements is reduced. It was also the cause.

On the other hand, in the prior art shown in FIG. 4, even if the flange portions 43A and 43B are formed, the end of the diffusion layer 44 is partitioned by the vertical side surface of the insulating film filling the vertical trench isolation region 43, and thus the element is formed. Even if the stress is relieved at the end of the diffusion layer only because the isolation region has the flange portions 43A and 43B rather than the simple vertical trench, the surface portion of the diffusion layer end and the substrate and the insulating film are separated at a right angle. There is no change in that stress is generated in the part where As a result, thinning occurs by suppressing the silicide reaction at the end of the diffusion layer, and the resistance increases. Furthermore, when the element isolation width is narrow, the silicide layer that has grown up from the diffusion layers at both ends of the trench is grown on the insulating film of the trench by the silicide layer, as if a leak current between the diffusion layers occurred in the element isolation method by the local diffusion method. However, the leak current between the diffusion layers cannot be avoided.

Therefore, an object of the present invention is to provide a semiconductor device and its manufacturing method which can prevent the occurrence of leak current between elements without increasing the resistance of the silicide layer.

[0008]

A feature of the present invention is that a single crystal silicon substrate, an element isolation trench formed in the single crystal silicon substrate, and a sidewall of the element isolation trench are formed by deposition. Polysilicon sidewall,
A semiconductor device has an insulating film formed on a side surface of the polysilicon sidewall and a silicide layer formed on a surface of the single crystal silicon substrate and having an end portion formed on the polysilicon sidewall. A diffusion layer serving as a source or drain region of the MOSFET may be formed under the silicide layer.

Another feature of the present invention is the step of forming an element isolation trench in a silicon substrate, and the anisotropic dry etching by forming a silicon film on the silicon substrate and masking the gate electrode formation region. By forming the gate electrode from the silicon film, and simultaneously forming from the silicon film a sidewall whose upper end has an arcuate shape (R) on the side wall of the isolation trench.
A sidewall insulating film is formed from the insulating film on the side surface of the gate electrode by depositing an insulating film and performing anisotropic dry etching, and at the same time, the side surface of the sidewall in the element isolation trench is covered with the insulating film. And a step of forming a silicide layer on the upper surface of the side wall of the diffusion layer to be a source or drain region, the end of which is located above the sidewall, and at the same time, forming a silicide layer on the upper surface of the gate electrode. Is coated with an interlayer insulating film to form contact holes and wirings. Here, it is preferable that the silicon substrate is a single crystal silicon substrate and the silicon film is a polysilicon film.

Another feature of the present invention is the step of forming an element isolation trench in a silicon substrate, and the step of forming the element isolation trench by forming a silicon film on the silicon substrate and performing anisotropic dry etching. Upper surface of the silicon substrate and the sidewall by depositing an insulating film and performing anisotropic dry etching to form a sidewall having an arcuate (R) upper end on the sidewall of Removing the upper insulating film and leaving the insulating film on the side surface of the sidewall in the element isolation trench; and selectively growing an insulating layer only on the insulating film on the side surface of the sidewall. And a step of forming a silicide layer from the upper surface of the silicon substrate to the arcuate upper end of the sidewall. In the manufacturing method. Here, the insulating layer is preferably a silicon oxide layer formed by a liquid phase oxide film growth method.

[0011]

According to the present invention described above, the sidewall having the arcuate (R) upper end is formed from the silicon film on the sidewall of the isolation trench formed in the silicon substrate.
Therefore, it can be considered that the silicon substrate and the silicon film form a trench in which R is formed around the opening, and the end of the silicide layer is located above the side wall of the silicon film. The thickness of the silicide layer does not become thin.

That is, in the present invention, unlike the conventional insulating film, a projection shape or a square shape such as a bird's beak does not exist at the boundary of the semiconductor substrate. In the present invention, the concentration of stress does not occur due to the R of the silicidable material around the opening, so that a silicide having a uniform film thickness can be formed over the entire surface of the diffusion layer without hindering the silicidation reaction. As a result, the resistance of the silicide layer does not increase even if the diffusion layer width is narrowed due to the miniaturization of the element, and stable formation of the silicided diffusion layer becomes possible.

Further, as shown in FIGS. 3 and 4 of the prior art, the silicide is not formed in a state where the isolation region is completely filled with the insulating film. In the present invention, the element isolation trench is formed of the insulating film when the silicide is formed. Since it is possible not to completely fill the gap, even if the separation width is narrowed and the distance between the diffusion layers is narrowed, the leakage current between the diffusion layers caused by the rise of the silicide on the insulating film is suppressed. be able to.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the steps of manufacturing a semiconductor device according to the first embodiment of the present invention.

First, in FIG. 1A, an N type well 2 and a P type well 3 are formed in a P type single crystal silicon substrate 1 to form a channel portion, and a film thickness of 7 nm is formed on a main surface 1S thereof.
A gate insulating film 4 made of a silicon oxide film is formed.
Then, an element isolation trench 10 deeper than the well is formed inside the main surface 1S to separate both wells, and boron ion implantation and annealing are performed to prevent P ⁺ between elements for preventing element leakage.
The channel stopper region 5 is formed.

Next, referring to FIG. 1B, a film thickness of 1 is formed on the substrate.
After forming a 50 nm poly-silicon film and forming a photoresist pattern (not shown) only on the portion of the polysilicon film to be the gate electrode, anisotropic dry etching is performed on the entire surface except the masked portion. A polysilicon gate electrode 6 is formed, and at the same time, a device isolation trench 1 is formed.
A polysilicon sidewall 11 having an arc R at the upper end is formed on the sidewall of 0.

Here, the curvature of R depends on the film thickness of the polysilicon film. The thickness of the polysilicon film is at least 50n
m, that is, the radius of curvature R needs to be at least 50 nm. As a result, there is no portion having a right angle that suppresses silicidation as in the flange type structure shown in FIG. 4 of the prior art, and the silicidation reaction is promoted around the diffusion layer (edge of diffusion layer).

The reason why the sidewall having R is formed of a silicon film such as a polysilicon film instead of an insulating film is that a refractory metal such as titanium (Ti) is deposited on silicon by sputtering or the like and reacted. This is because it is necessary to silicify the upper portion of the sidewall. That is, when the side wall is formed of the insulating film, as described with reference to FIG. 4, since the silicon substrate is formed at a right angle by the side wall of the trench, stress is applied to the pointed portion and the silicide is hard to be formed. .

When the N-type well and the P-type well are used as in this embodiment, for example, an N-type well having the same concentration as the N-type well 3 or a slightly lower concentration than the N-type well 3 is deposited, After the polysilicon side wall 11 is formed by anisotropic dry etching, heat treatment is performed at 800 ° C. for several tens of seconds to diffuse the boron in the P-type well 3 to the polysilicon side wall 11 to be deposited thereon to form P. Make it a mold. As a result, the N-type polysilicon side wall 11N is formed on the side wall of the N-type well 2 and the P-type polysilicon side wall 11P is formed on the side wall of the P-type well 3.
Are adhered and formed.

Next, referring to FIG. 1C, a silicon oxide film having a thickness of 70 nm is deposited by a high temperature vapor phase epitaxy method and anisotropic dry etching is performed on the entire surface to oxidize sidewalls on the side surfaces of the gate electrode 6. The film 7 is formed, and at the same time, only the side surface of the polysilicon sidewall 11 in the element isolation trench 10 is covered with the silicon oxide film 12.

Next, referring to FIG. 1D, a pair of P-type diffusion layers 13P are formed in the N-type well 2 to serve as the source and drain regions of the P-channel MOSFET.
A pair of N type diffusion layers 13N are formed in the type well 3 to serve as the source and drain regions of the N channel MOSFET. The P-type diffusion layer 13P forms a PN junction with the N-type well 2 and the N-type polysilicon sidewall 11N, and the N-type diffusion layer 13N forms a PN junction with the P-type well 3 and the P-type polysilicon sidewall 11P. . Further, in order to promote the silicide reaction in the next step, arsenic ion implantation is performed with a dose amount that is one digit less than the dose amount of the source and drain regions.

Then, Ti (titanium) is used as the refractory metal.
Was sputtered to form a film.
After annealing for 30 seconds, TiSi _{2 is formed} only on the upper surface of the P type diffusion layer 13P, the exposed surface of the silicon substrate including the upper surface of the N type diffusion layer 13N and the upper surface of the polysilicon gate electrode 6.
Forming a silicide layer of.

After that, the nitrided Ti on the silicon oxide film is removed by ammonia hydrogen peroxide, and then 8
By heat treatment at 40 ° C. for 10 seconds, the silicide layer 14 having a low resistance is formed. Since the element isolation trench is not completely filled with the insulating film when the silicide layer is formed, the silicide does not cause a leak current that rises up onto the insulating film.

Next, in FIG. 1E, a film thickness of 10 is formed on the entire surface.
An interlayer insulating film 17 is formed by depositing a 0 nm silicon oxide film and depositing a 1 μm thick BPSG film thereon.
Reflow is performed at 700 ° C. In this embodiment, the gap between the silicon oxide films 12, 12 in the trench is filled only by the interlayer insulating film 17, so that the cavity 21 can be generated. Since air has a lower dielectric constant than the silicon oxide film, the parasitic capacitance can be reduced by the amount of the cavity 21 generated. Then, contact holes reaching the respective diffusion layers and gate electrodes are provided in the interlayer insulating film 17, the contact holes are filled with tungsten 18 and etched back, and then aluminum wirings 19 connected to the respective tungsten 18 are formed. In the first embodiment, the polysilicon side wall 11 and the gate electrode 6 can be simultaneously formed in one polysilicon deposition step and one anisotropic dry etching step.

FIG. 2 is a cross-sectional view showing the process sequence of manufacturing a semiconductor device according to the second embodiment of the present invention. Note that, in FIG. 2, portions having the same or similar functions as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted as much as possible.

First, in FIG. 2A, a thin insulating film (not shown) having a film thickness of 10 nm is formed on the main surface 1S of the P-type single crystal silicon substrate 1, and then an element isolation trench 10 is formed to form P. ^{A +} type channel stopper region 5 is formed.

Next, referring to FIG. 2B, a film thickness of 1 is formed on the substrate.
A polysilicon film having a thickness of 00 nm is formed, and anisotropic dry etching is performed on the entire surface to remove the polysilicon film and the insulating film on the surface to leave the polysilicon film only on the sidewalls of the element isolation trenches 10. A polysilicon sidewall 11 having an arc R at its upper end is formed.

Then, a thin silicon oxide film is deposited and anisotropic dry etching is performed on the entire surface to remove the planar silicon oxide film, and only on the side surface of the polysilicon side wall 11 in the element isolation trench 10. Are covered with a silicon oxide film 12.

Next, in FIG. 2C, a silicon oxide layer 20 is selectively formed only on the silicon oxide film 12 in the trench by a liquid phase oxide film growth method.

In this liquid phase growth method, a semiconductor wafer is placed in a solution of H ₂ SiF _{6 in} which silica is dissolved in a supersaturated state, and H ₃ is added.
A chemical reaction is caused by dropping BO ₃ , so that the silicon oxide layer 20 is formed on the semiconductor wafer.
It is a method of depositing only on the top. The liquid phase grown silicon oxide layer 20 can be formed at a low temperature and has a very small stress. Moreover, since the growth selectively occurs only on the silicon oxide film 12, the groove of the element isolation trench 10 can be easily filled. Since the silicon oxide layer 20 selectively grows only on the silicon oxide film 12, the upper portion of the element isolation trench is not filled with the silicon oxide layer 20.

Next, in FIG. 2D, an N type well 2 and a P type well 3 are formed, and ion implantation for forming a channel region is performed. Then, heat treatment is performed at 800 ° C. for several tens of seconds to diffuse boron in the P-type well 3 into the polysilicon side wall 11 to be deposited thereon to make it P-type.
As a result, the N-type polysilicon sidewall 11N is deposited on the sidewall of the N-type well 2 and the P-type polysilicon sidewall 11P is deposited on the sidewall of the P-type well 3. After that, the gate oxide film 4 is set to 7 nm.
To a thickness of 150 nm, polysilicon is deposited to a thickness of 150 nm, and a polysilicon gate electrode 6 is formed by a photoresist process and a dry etching process. After that, a silicon oxide film with a film thickness of 70 nm is deposited by high temperature vapor phase epitaxy,
By performing anisotropic dry etching on the entire surface, sidewall oxide film 7 is formed on the side surface of gate electrode 6. afterwards,
Arsenic ions are formed with a dose that is one order of magnitude less than the dose of the source and drain regions in order to form the P-type diffusion layer 13P and the N-type diffusion layer 13N to be the source and drain regions of each MOSFET and to accelerate the silicide reaction. Make an injection. Then, Ti is sputter-deposited and annealed in a nitrogen atmosphere at 690 ° C. for 30 seconds to expose the surface of the silicon substrate, that is, the upper surfaces of the P-type diffusion layer 13P and the N-type diffusion layer 13N and the polysilicon gate electrode 6. A TiSi ₂ silicide layer is formed only on the upper surface. Then, the nitrided Ti on the silicon oxide film is removed by ammonia hydrogen peroxide. Further, heat treatment is applied at 840 ° C. for 10 seconds to form the silicide layer 14 having a low resistance.

Next, in FIG. 2E, an interlayer insulating film 17 is formed by the same process as in FIG. 1E, a contact hole is provided therein, and the contact hole is filled with tungsten 18 to form an aluminum wiring 19. .

In this second embodiment, polysilicon is deposited for forming the polysilicon sidewall 11 and for forming the gate electrode 6, respectively.
Although a number of anisotropic dry etching steps are required, there is an advantage that each can have an optimum film thickness. Further, in the second embodiment, since the liquid phase growth silicon oxide film 20 is formed in advance, the cavity 21 (FIG. 1 (E)) is not generated unlike the first embodiment. Therefore, the second embodiment is suitable for a semiconductor device in which it is important to finally completely fill the trench with an interlayer insulating film or the like to ensure the insulation rather than to reduce the parasitic capacitance.

[0035]

According to the present invention, the suppression of silicidation due to stress, which has been a problem in the formation of a Ti silicide layer by the salicide process, can be eliminated, and a stable silicide layer can be formed even in a narrow diffusion layer. In addition, the leakage current between the diffusion layers can be suppressed, which has the effect of improving the yield as well as miniaturization of the device.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view showing a conventional technique.

FIG. 4 is a cross-sectional view showing another conventional technique.

[Explanation of symbols]

1 Silicon (Si) Substrate 1S Main Surface 2 N-type Well 3 P-type Well 4 Gate Insulating Film 5 P ⁺ Channel Stopper Region 6 Polysilicon Gate Electrode 7 Sidewall Oxide Film 10 Element Isolation Trench 11 Polysilicon Sidewall 11N N-type Poly Silicon sidewall 11P P-type polysilicon sidewall 12 Silicon oxide film 13P P-type diffusion layer 13N N-type diffusion layer 14 Silicide layer 17 Interlayer insulating film 18 Tungsten 19 Aluminum wiring 20 Liquid phase silicon oxide layer 21 Cavity in the interlayer insulating film 31 , 41 Silicon substrate 31S, 41S Main surface of silicon substrate 33 Field oxide film 33A Bird's beak 34 Source / drain diffusion layer 35 Silicide layer 36,46 Gate insulating film 37,47 Polysilicon gate electrode 38,48 Sidewall oxide film 43 Trench isolation region 43A, 43B Flange portion made of silicon oxide film in the trench isolation region

Claims (7)

(57) [Claims] 1. A single crystal silicon substrate, an element isolation trench formed in the single crystal silicon substrate, a polysilicon sidewall formed by adhering to a sidewall of the element isolation trench, and the polysilicon. A semiconductor device comprising: an insulating film formed on a side surface of a sidewall; and a silicide layer formed on a surface of the single crystal silicon substrate and having an end portion formed on an upper portion of the polysilicon sidewall. 2. The semiconductor device according to claim 1, wherein a diffusion layer is formed under the silicide layer. 3. The semiconductor device according to claim 3, wherein the diffusion layer is a source or drain region of an insulated gate field effect transistor. 4. A gate is formed by forming an element isolation trench in a silicon substrate, forming a silicon film on the silicon substrate, and masking the gate electrode formation region to perform anisotropic dry etching. Simultaneously with forming the electrode from the silicon film, a step of forming from the silicon film a sidewall having an arcuate upper end on the sidewall of the isolation trench, and depositing an insulating film and performing anisotropic dry etching Thus, a sidewall insulating film is formed from the insulating film on the side surface of the gate electrode, and at the same time, the side surface of the sidewall in the isolation trench is covered with the insulating film, and the upper surface of the diffusion layer to be the source or drain region. A silicide layer whose end is located above the sidewall, and at the same time, a silicide layer is formed on the upper surface of the gate electrode. A method of manufacturing a semiconductor device, comprising: a step of forming a side layer; and a step of covering the whole with an interlayer insulating film to form a contact hole and a wiring. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the silicon substrate is a single crystal silicon substrate, and the silicon film is a polysilicon film. 6. A step of forming an element isolation trench in a silicon substrate, and a silicon film is formed on the silicon substrate and anisotropic dry etching is performed to form an upper end portion on a sidewall of the element isolation trench. Forming an arc-shaped sidewall from the silicon film; and depositing an insulating film and performing anisotropic dry etching to remove the insulating film on the upper surfaces of the silicon substrate and the sidewall. A step of leaving the insulating film on the side surface of the sidewall in the element isolation trench,
A step of selectively growing an insulating layer only on the insulating film on the side surface of the sidewall; and a step of forming a silicide layer from the upper surface of the silicon substrate to the arcuate upper end portion of the sidewall. A method for manufacturing a characteristic semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the insulating layer is a silicon oxide layer formed by a liquid phase oxide film growth method.