JP5549410B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device having a trench isolation structure.

  Along with the reduction in the size of semiconductor elements, the separation between elements has become minute. The so-called LOCOS (Local Oxidation of Silicon) method, which defines the isolation region by thermally oxidizing the silicon substrate, always has a large bird's beak, and the fine active region sandwiched between the isolation regions has the disadvantage of disappearing due to this bird's beak. there were. In order to solve this, it is widely known that the suppression of bird's beak using a trench isolation method is a common solution.

In trench isolation, an insulating film is embedded in a groove provided in a silicon substrate. After the filling, the insulating film is etched to the vicinity of the main surface of the silicon. Dry etching and CMP methods are widely used for planarizing the buried oxide film.
In the actual semiconductor device, as shown in FIG. 23, the active region 11 and the isolation region 21a of the semiconductor substrate 10 are mixed, but the buried oxide film forming the isolation region 21a is raised from the main surface of the active region 11. I have to. 21b shows a bird's beak. In this structure, as with the LOCOS isolation, it is possible to suppress the generation of parasitic MOS by raising the isolation oxide film from the silicon substrate 10, and when the edge shape at the end of the trench opening becomes steep, the breakdown voltage with the gate is reduced. It was possible to prevent.

JP 09-252129 A JP-A-11-177084 JP 08-335700 A JP 59-086241 A JP-A-10-223747

However, such conventional devices have the following problems.
FIG. 24 is a cross-sectional view of the conventional semiconductor device in the gate width direction. As indicated by the arrows in the figure, in the conventional example, the effective gate width becomes narrow and the drain current decreases.
FIG. 25 shows a cross-sectional view in the direction of the gate width of another conventional semiconductor device. In such a conventional example, the n-type layer 16 is formed on the p-type layer 15 of the semiconductor substrate 10, for example. At this time, since the junction edge of the n-type layer (reverse conductivity type layer) under the salicide 80 is approaching, the depletion layer tends to approach the salicide and the breakdown voltage is lowered.

  The conventional trench isolation has a structure as described above, so that the narrow channel effect is likely to appear, and the transistor threshold is likely to rise as the transistor is miniaturized, the threshold is difficult to control, and the drain current does not flow. I tend to be in a state.

  The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to obtain an improved semiconductor device and a method for manufacturing the same by preventing a decrease in drain current of the transistor.

A manufacturing method of a semiconductor device according to claim 1 of the present invention is as follows:
Forming a trench isolation groove on the main surface of the semiconductor substrate;
Forming a first insulating film directly on the inner wall of the trench isolation trench;
Forming a second insulating film as an embedding material including a material different from the first insulating film so as to embed the trench isolation trench on the main surface of the semiconductor substrate;
Etching back the second insulating film to remove the second insulating film on the main surface of the semiconductor substrate and leaving it as a filling material in the trench isolation trench;
The first insulating film has a predetermined thickness so that the upper surface of the first insulating film is lower than the upper surface of the filling material and the upper surface of the first insulating film is lower than the main surface of the semiconductor substrate. And a step of removing.

According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method according to the first aspect ,
After the step of removing the first insulating film by a predetermined thickness,
Forming a third insulating film on the main surface of the semiconductor substrate;
Forming a conductive film on the third insulating film, the first insulating film, and the filling material;
Patterning the conductive film and the third insulating film to form a gate electrode and a gate insulating film;
Forming a fourth insulating film on the main surface of the semiconductor substrate including the gate electrode;
The fourth insulating film is patterned to form a side wall insulating film on the side wall of the gate electrode, and a side wall insulating film is formed so as to cover the inner wall of the trench isolation trench above the first insulating film. And a forming step.

According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method according to the second aspect ,
After the step of forming the sidewall insulating film,
Forming a refractory metal film on the main surface of the semiconductor substrate;
And a step of heat-treating the refractory metal film to form a salicide structure on the main surface of the semiconductor substrate exposed from the sidewall insulating film.

According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method according to any one of the first to third aspects,
The semiconductor substrate is a silicon substrate, the first insulating film contains nitrogen, and the filling material is a silicon oxide film.

  According to the present invention, it is possible to obtain a semiconductor device having improved characteristics in which the trench isolation structure is improved and the drain current of the transistor is increased or the junction breakdown voltage is improved, and a method for manufacturing the same.

1 is a partial plan view of a semiconductor device according to a first embodiment of the present invention. The trench partial sectional view of FIG. 1 is a partial plan view of a MOSFET semiconductor device according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view along the trench crossing line of FIG. 3. Sectional drawing explaining the effect | action of Embodiment 1. FIG. Sectional drawing which shows the manufacturing method of Embodiment 1 of this invention. FIG. 6 is a partial cross-sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 9 is a partial plan view of a MOSFET semiconductor device according to a third embodiment of the present invention. FIG. 9 is a cross-sectional view taken along the trench crossing line of FIG. 8. Sectional drawing explaining the effect | action of the semiconductor device by Embodiment 3 of this invention. FIG. 9 is a partial plan view of a semiconductor device according to a fourth embodiment of the present invention. The fragmentary sectional view of the MOSFET semiconductor device by Embodiment 4 of this invention. Sectional drawing which shows the manufacturing method of Embodiment 4 of this invention. FIG. 10 is a partial cross-sectional view of a MOSFET semiconductor device according to a fifth embodiment of the present invention. FIG. 10 is a partial cross-sectional view of a MOSFET semiconductor device according to a sixth embodiment of the present invention. FIG. 10 is a partial cross-sectional view illustrating the operation of a semiconductor device according to a sixth embodiment of the present invention. FIG. 10 is a partial cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention. Sectional drawing which shows the manufacturing method of Embodiment 7 of this invention. FIG. 10 is a partial sectional view of a MOSFET semiconductor device according to an eighth embodiment of the present invention. FIG. 10 is a partial cross-sectional view of a semiconductor device according to a ninth embodiment of the present invention. Sectional drawing which shows the manufacturing method of Embodiment 9 of this invention. FIG. 10 is a partial sectional view of a MOSFET semiconductor device according to a tenth embodiment of the present invention. The fragmentary sectional view in alignment with the trench transverse line of the semiconductor device of a prior art example. FIG. 9 is a partial cross-sectional view of a trench for explaining the operation of a conventional semiconductor device. The fragmentary sectional view of the MOSFET semiconductor device of a prior art example.

Embodiments of the present invention will be described below. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.
Embodiment 1 FIG.
1 and 2 are partial views of the semiconductor device according to the first embodiment of the present invention. FIG. 1 is a plan view and FIG. 2 is a sectional view taken along line II-II in FIG.
1 and 2, reference numeral 10 denotes a semiconductor substrate, for example, a silicon substrate, 11 an active region thereof, 20 a trench, and 21 a filling material for forming a trench isolation region. The present embodiment is characterized in that the entire surface of the trench filling material 21 is lower by a predetermined amount than the main surface of the semiconductor substrate 10 as shown in the cross-sectional view of FIG. The step for dropping the predetermined amount is about 2 to 5 nm. Then, the step is left after the gate oxidation.

Further, as shown in FIG. 2, the cross section of the trench 20 has a shape that narrows downward and widens upward.
The main surface of the semiconductor substrate 10 and the side surface where the semiconductor substrate 10 contacts the trench filling material 21 form an obtuse angle, and a curved surface is formed from the main surface to the side surface. That is, the edge of the semiconductor substrate is rounded in the trench opening.

3 and 4 are views showing the structure of the MOSFET according to the present embodiment, FIG. 3 is a plan view, and FIG. 4 is a sectional view taken along line IV-IV in FIG.
3 and 4, reference numeral 12 denotes a source or drain region, 13 denotes a source or drain contact, 30 denotes a gate insulating film (oxide film), and 40 denotes a gate electrode.
According to the application example to the MOSFET as shown in FIGS. 2 and 4, the driving capability of the MOSFET can be increased.
Note that the gate electrode 40 may have not only a single layer as shown, but also a structure of two or more layers such as polycide.

FIG. 5 shows a cross-sectional view in the direction of the gate width of the semiconductor device in this embodiment.
As shown by the arrows in the figure, in this embodiment, the effective gate width is wider than that of the conventional example shown in FIG. 24, and the drain current is increased accordingly. In addition, an increase in threshold due to back bias is suppressed, and a MOSFET that is less susceptible to source resistance can be realized.

FIG. 6 is a partial cross-sectional view for explaining an example of a method for manufacturing a semiconductor device in the present embodiment.
As shown in FIG. 6A, a mask of, for example, a nitride film 50 (or oxide film) is formed on the surface of the semiconductor substrate 10, and trench etching is performed through this mask pattern to form the trench 20, and the inner wall of the trench Then, an embedding material (oxide film) 60 is deposited.
Next, from FIG. 6A, the excess filling material 60 is removed by dry etching or CMP to form the shape shown in FIG. 6B. Next, a part of the upper layer portion of the embedding material 60 is dropped from that of FIG. 6B with hydrofluoric acid to form the shape shown in FIG.
Next, from FIG. 6C, the nitride film 50 is removed with hot phosphoric acid to form the shape of FIG. 6D. Finally, as shown in FIG. 6E, the upper layer portion of the embedding material 60 is dropped by a predetermined amount with hydrofluoric acid from that of FIG. 6D, and this embodiment similar to that shown in FIG. Get shape. Note that a predetermined amount of drop from the substrate surface of the burying material 60 is about 2 to 5 nm so that the step remains even after gate oxidation.

  Here, although the impurities of the silicon substrate 10 are not specified, for example, doping may be performed by oblique ion implantation after oxidizing the inner wall of the trench, or doping may be performed before first depositing the nitride film / oxide film mask. May be deeply diffused by heat treatment.

As described above, the semiconductor device of the present embodiment includes the trench filling material (trench isolation region) 21 that isolates the active region on the main surface of the semiconductor substrate 10. The trench filling material is formed so as to drop at a predetermined height from the main surface of the semiconductor substrate at least at a portion where the surface of the trench filling material is in contact with the semiconductor substrate 10.
Further, a gate insulating film (oxide film) 30 is formed on the main surface of the semiconductor substrate 10, and a gate electrode (conductive film) 40 is continuously formed on the surface of the insulating film 30 and the trench filling material 21. Yes.

  According to this embodiment, it is possible to increase the drain current (Id) of the transistor, reduce the substrate effect of the transistor, and further suppress the stress / interface state.

Embodiment 2. FIG.
FIG. 7 is a cross-sectional view for explaining a semiconductor device according to the second embodiment of the present invention. Similar to FIG. 4, this corresponds to a cross section taken along line IV-IV in the plan view of FIG. This embodiment is a further improvement of the first embodiment.
In FIG. 7, reference numerals 14 a, 14 b, and 14 c denote specific impurity layers formed at different depths in the semiconductor substrate 10.
As described above, this embodiment is characterized in that the impurity concentration in the silicon substrate 10 provided with the trench 20 is nonuniform. After the trench 20 is completed, impurity layers 14a, 14b, and 14c (ion implantation layers) are formed by ion implantation. Thereby, punch-through to adjacent MOSFETs can be suppressed. The number of ion-implanted layers is not limited as long as it is two or more.
Further, an epitaxial growth substrate may be used as the semiconductor substrate 10.

As described above, in the semiconductor device according to the present embodiment, the plurality of impurity layers 14 a, 14 b, and 14 c are formed by ion implantation at different predetermined depths of the semiconductor substrate 10.
According to this embodiment, it is possible to increase the drain current of the transistor, reduce the substrate effect of the transistor, suppress the punch through of the transistor, and further suppress the stress / interface state.

Embodiment 3 FIG.
8 and 9 are diagrams for explaining the semiconductor device according to the third embodiment of the present invention. FIG. 8 is a plan view of the semiconductor device in which the MOSFET is formed, and FIG. 9 is a sectional view taken along line IX-IX in FIG. A cross-sectional view is shown. However, FIG. 8 is a plan view before forming the sidewalls and salicide.
8 and 9, 12 is a source or drain region, 13 is a source or drain contact, 30 is a gate insulating film (oxide film), 40 is a gate electrode, 70 is a side wall of the gate electrode 40, and 71 is a side. An insulating film (side wall on the side surface of the semiconductor substrate 10) formed together with the wall 70, 80 is a salicide.
In this embodiment, salicide is applied to the first embodiment.
The salicide 80 is made by sputtering a metal typified by Ti, Co, Ni, W or the like and heating the lamp to cause the silicon substrate 10 to react to form a salicide structure.

This embodiment is characterized in that the deterioration of the junction breakdown voltage as seen in the conventional example is not observed.
This will be described with reference to FIG. FIG. 10 is a partial enlarged cross-sectional view for explaining the operation of the semiconductor device according to this embodiment.
In FIG. 10, 10 is a semiconductor substrate, 11 is an active region thereof, 15 is a p-type substrate region, 16 is an n-type conductive layer of the active region 11, 20 is a trench, 21 is a trench filling material, 71 Indicates an insulating film, and 80 indicates salicide.
As shown in FIG. 10, in this embodiment, since the trench filling material 21 falls into the trench 20, the n-type conductive layer 16, which is a reverse conductivity type layer, enters deeply at the trench edge, and further the insulating film 71. Since salicide 80 is formed at a position far from the bonding edge, the breakdown voltage increases.

  As described above, in the semiconductor device according to the present embodiment, salicide 80 is formed in a predetermined region adjacent to trench filling material 21 on the main surface of semiconductor substrate 10, and the portion where trench filling material 21 falls is formed. An insulating film 71 continuous with the salicide 80 is formed on the surface of the semiconductor substrate 10.

  According to this embodiment, it is possible to improve the salicide junction breakdown voltage and to suppress the stress / interface state.

  In the present invention, the structure of FIG. 3 and the structure of FIG. 8 show different parts of the same semiconductor device. That is, the first and third embodiments are realized by different parts of the same semiconductor device.

Embodiment 4 FIG.
FIG. 11 is a view for explaining the semiconductor device according to the fourth embodiment of the present invention, and shows a cross-sectional view taken along a trench transverse line.
In FIG. 11, reference numeral 90 denotes a recess formed as a depression at the outer edge of the trench.
In this embodiment, the surface of the trench filling material 21 is formed at substantially the same height (level) as the surface of the semiconductor substrate 10, but at the edge of the surface in contact with the semiconductor substrate 10, A recess 90 is formed to be lower than the main surface.

FIG. 12 is a cross-sectional view showing the structure of the MOSFET according to the present embodiment.
The effect obtained by the semiconductor device shown in FIG. 12 compared to the semiconductor device shown in FIGS. 3 and 4 of the first embodiment is that the gate capacitance can be reduced. This is because the bulk of the surface of the embedded material other than the trench edge is high, thereby reducing the parasitic capacitance with the silicon substrate 1 and increasing the overall speed of the semiconductor device.

FIG. 13 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to this embodiment.
FIG. 13A shows a state immediately after depositing a filling material (oxide film) 60 through trench etching as in FIG. FIG. 13B also shows a state in which the embedded material 60 is flattened by dry etching or CMP, as in FIG. 6B. Next, when the nitride film 50 is removed with hot phosphoric acid as shown in FIG. 13C and the embedding material 60 is dissolved with hydrofluoric acid as shown in FIG. The recess 90 can be easily formed.

  As described above, in the semiconductor device according to the present embodiment, the surface of trench filling material (isolation region) 21 is formed at substantially the same height as the main surface of semiconductor substrate 10, and trench filling material 21 is formed on the semiconductor substrate. It is formed so as to drop a predetermined height only at a portion in contact with 10.

  According to this embodiment, it is possible to increase the drain current of the transistor, reduce the substrate effect of the transistor, reduce the parasitic capacitance between the transfer gate and the substrate, and further suppress the stress / interface state.

Embodiment 5 FIG.
FIG. 14 is a cross-sectional view for explaining the semiconductor device according to the fifth embodiment of the present invention, and shows a cross-sectional view taken along a trench transverse line.
In FIG. 14, 14 a, 14 b and 14 c indicate specific impurity layers in the semiconductor substrate 10.
Thus, in this embodiment, in the structure of the fourth embodiment, the impurity concentration in the silicon substrate 10 provided with the trench 20 is made nonuniform. After the trench 20 is completed, impurity layers 14a, 14b, and 14c (ion implantation layers) are formed by ion implantation. Thereby, punch-through to adjacent MOSFETs can be suppressed. Furthermore, in addition to the same effects as in the fourth embodiment, it is possible to reduce the parasitic capacitance.
An epitaxial growth substrate may be used for the semiconductor substrate 10. Further, the number of ion-implanted layers is not limited as long as it is two or more.

  According to this embodiment, the drain current of the transistor is increased, the substrate effect of the transistor is reduced, the punch through of the transistor is suppressed, the parasitic capacitance between the transfer gate and the substrate is reduced, and the stress and interface state are suppressed. Can be planned.

Embodiment 6 FIG.
FIG. 15 is a diagram for explaining the semiconductor device according to the sixth embodiment of the present invention, and shows a cross-sectional view taken along a trench transverse line.
In FIG. 15, reference numeral 90 denotes a recess (sag) at the outer edge of the trench. Reference numeral 71 denotes an insulating film right (oxide film) filling the recess 90, and 80 denotes salicide.
In this embodiment, salicide is applied to the fourth embodiment.

FIG. 16 is a partially enlarged view for explaining the operation of the semiconductor device according to this embodiment.
In FIG. 16, 10 is a semiconductor substrate, 11 is its active region, 15 is a p-type substrate region, 16 is an n-type conductive layer of the active region 11, 20 is a trench, 21 is a trench filling material, 90 Denotes a recess at the edge of the trench filling material, 71 denotes an oxide film filling the recess 90, and 80 denotes salicide.
As shown in FIG. 16, in this embodiment, a recess 90 is formed and falls at the edge of the trench filling material 21, and further, this recess is filled with an insulating film (oxide film) 71. For this reason, the n-type conductive layer 16, which is a reverse conductivity type layer, penetrates deeply at the trench edge, and the insulating film (oxide film) 71 blocks this drop, so that the salicide 80 becomes far from the junction edge and is depleted. The layer can be stretched, resulting in an increase in breakdown voltage.
The insulating film (oxide film) 71 can be formed simultaneously with the gate sidewall (oxide film) 70.

  As described above, in the semiconductor device of the present embodiment, the insulating film 71 continuous to the salicide 80 is formed on the surface of the semiconductor substrate 10 in the portion 90 where the trench filling material (isolation region) 21 falls, and the trench The insulating film 71 fills the portion 90 where the embedded material 21 has fallen.

  According to this embodiment, salicide junction breakdown voltage can be improved, parasitic capacitance between the transfer gate and the substrate can be reduced, and stress and interface states can be suppressed.

Embodiment 7 FIG.
FIG. 17 is a diagram for explaining the semiconductor device according to the seventh embodiment of the present invention, and shows a cross-sectional view taken along a trench crossing line.
In FIG. 17, 20 is a trench, 21 is a filling material (oxide film), 101 is a nitride film, and 91 is a recess (drop) in trench etching.

FIG. 18 is a partial cross-sectional view for explaining an example of a method of manufacturing a semiconductor device in this embodiment.
Referring to FIG. 18A, trench 20 is formed in semiconductor substrate 10 using nitride film 50 as a mask, and nitride film 100 is directly deposited on the inner wall of the trench. Further, as shown in FIG. 18B, an embedding material (oxide film) 60 is deposited thereon.

Next, the embedded material (oxide film) 60 is etched back by dry etch back or CMP to obtain the shape shown in FIG. Further, in FIG. 18D, the nitride film 50 is removed with hot phosphoric acid, and a predetermined amount of the nitride film 100 is removed. At this time, the nitride film 100 embedded in the inner wall falls to form a recess 91, and the shape of the nitride film 101 is completed.
As described above, this embodiment is characterized in that two types of filling materials inside the trench are used. As a result, for example, a recess (sag) 91 at the trench edge is realized due to a difference in etching rate between the filling material (oxide film) 60 and the nitride film 100.

  As described above, the semiconductor device according to the present embodiment includes the nitride film (first insulating film) 101 in which the trench isolation region is in contact with the semiconductor substrate 10 and falls from the main surface of the semiconductor substrate 10 by a predetermined height. The nitride film 101 is formed with an embedding material 21 filling the inside.

  According to this embodiment, it is possible to increase the drain current of the transistor, reduce the substrate effect of the transistor, and reduce the parasitic capacitance between the transfer gate and the substrate.

Embodiment 8 FIG.
FIG. 19 is a diagram for illustrating a semiconductor device according to an eighth embodiment of the present invention, and is a cross-sectional view showing a MOSFET structure.
In this embodiment, the salicide described in the third embodiment is applied to the seventh embodiment.
In FIG. 19, 101 is a nitride film formed on the inner surface of the trench, 21 is a trench filling material (trench oxide film) formed on the inner side, 91 is a recess formed by dropping the nitride film 101, and 71 is filling the recess. The insulating film (oxide film) 80 is salicide.
The salicide 80 is made by sputtering a metal typified by Ti, Co, Ni, W or the like and heating the lamp to cause the silicon substrate 10 to react to form a salicide structure.
With such a structure, the effect obtained by superimposing the effect of the salicide in the third embodiment and the effect of the trench edge drop in the seventh embodiment can be obtained, and the breakdown voltage can be further increased.
Note that other combinations may be used as long as the materials have different etching rates.

  According to this embodiment, it is possible to improve the salicide junction breakdown voltage and reduce the parasitic capacitance between the transfer gate and the substrate.

Embodiment 9 FIG.
FIG. 20 is a diagram for explaining the semiconductor device according to the ninth embodiment of the present invention, and shows a cross-sectional view taken along a trench transverse line.
In FIG. 20, 20 is a trench, 110 is a thin insulating film (oxide film) formed on the inner surface of the trench 20, 101 is a nitride film formed inside the insulating film (oxide film) 110, and 21 is a nitride film 101. The trench filling material which filled the inner side is shown. Reference numeral 92 denotes a recess at the trench edge formed by dropping the nitride film 101.
In this embodiment, the trench filling is made into three layers. This is because the nitride film 101 sticks directly to the edge of the trench when there are two layers of trench filling as in the eighth embodiment, which may cause stress on the inner wall, interface state, etc. This can be prevented by using three layers as shown in FIG.

FIG. 21 is a cross-sectional view for explaining an example of a method of manufacturing a semiconductor device in this embodiment.
FIG. 21A shows a state in which the semiconductor substrate 10 is trench-etched using the nitride film 50 as a mask, the inner wall of the trench is oxidized, and the nitride film 100 is further deposited. An embedding material (oxide film) 60 is deposited thereon as shown in FIG. 21B, and etch back is further performed as shown in FIG. Finally, as shown in FIG. 21 (d), the nitride film 50 is removed with hot phosphoric acid, and a predetermined amount of the nitride film 100 is removed to form a depression 92, leaving the nitride film 101, and the final shape of FIG. The structure shown in is obtained.

  As described above, in the semiconductor device of the present embodiment, the trench isolation region is divided into a thin insulating film (first insulating film) 110 (oxide film) in contact with the semiconductor substrate 10 and the thin insulating film 110. A nitride film (second insulating film) 101 that is formed in contact with the inner surface of the semiconductor substrate 10 and has a predetermined height dropped from the main surface of the semiconductor substrate 10, and an embedding material 21 that fills the inner side of the nitride film 101.

  According to this embodiment, it is possible to increase the drain current of the transistor, reduce the substrate effect of the transistor, reduce the parasitic capacitance between the transfer gate and the substrate, and further suppress the stress / interface state.

Embodiment 10 FIG.
FIG. 22 is a diagram for illustrating the semiconductor device according to the tenth embodiment of the present invention, and is a cross-sectional view showing the MOSFET structure.
In FIG. 22, 20 is a trench, 110 is a thin insulating film (oxide film) covering the inner surface of the trench, 101 is a nitride film covering the inner surface, 21 is a trench filling material, 92 is a recess (drop) at the trench edge, 71 Denotes an insulating film (oxide film) filling the recess 92, and 80 denotes salicide.
In this embodiment, salicide is applied to the ninth embodiment. Such a composite structure has an effect of further increasing the breakdown voltage.

  10 semiconductor substrate, 11 active region, 12 source or drain region, 13 source or drain contact, 14a, 14b, 14c impurity layer (ion implantation layer), 15 p-type substrate region, 16 n-type conductive layer, 20 trench, 21 trench Embedded material (trench isolation region), 30 gate insulating film, 40 gate electrode, 50 nitride film, 60 embedded material, 70 sidewall, 71 insulating film, 80 salicide, 90, 91, 92 recessed (recessed), 100, 101 Nitride film.

Claims (4)

Forming a trench isolation groove on the main surface of the semiconductor substrate;
Forming a first insulating film directly on the inner wall of the trench isolation trench;
Forming a second insulating film as an embedding material including a material different from the first insulating film so as to embed the trench isolation trench on the main surface of the semiconductor substrate;
Etching back the second insulating film to remove the second insulating film on the main surface of the semiconductor substrate and leaving it as a filling material in the trench isolation trench;
The first insulating film has a predetermined thickness so that the upper surface of the first insulating film is lower than the upper surface of the filling material and the upper surface of the first insulating film is lower than the main surface of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising the step of removing. After the step of removing the first insulating film by a predetermined thickness,
Forming a third insulating film on the main surface of the semiconductor substrate;
Forming a conductive film on the third insulating film, the first insulating film, and the filling material;
Patterning the conductive film and the third insulating film to form a gate electrode and a gate insulating film;
Forming a fourth insulating film on the main surface of the semiconductor substrate including the gate electrode;
The fourth insulating film is patterned to form a side wall insulating film on the side wall of the gate electrode, and a side wall insulating film is formed so as to cover the inner wall of the trench isolation trench above the first insulating film. The method for manufacturing a semiconductor device according to claim 1, further comprising a forming step. After the step of forming the sidewall insulating film,
Forming a refractory metal film on the main surface of the semiconductor substrate;
The method for manufacturing a semiconductor device according to claim 2, further comprising: heat-treating the refractory metal film to form a salicide structure on the main surface of the semiconductor substrate exposed from the sidewall insulating film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate, the first insulating film contains nitrogen, and the filling material is a silicon oxide film. 5.

Images