JPH0621452A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the gate width of a field effect transistor without reducing the integration degree of the LSI comprising the transistors, by making the cross section of the active region of the transistor convex. CONSTITUTION:In a field effect transistor, first, a silicon oxide film 2 is formed on a silicon substrate 1, and thereon, silicon nitride film 3 is formed. Then, after applying a resist 4 thereto extensively, the silicon substrate 1 is etched to a predetermined depth while removing the nitride film 3 and the silicon oxide film 2, and in the region to be changed into the region for separating elements from each other, an opening part is formed, and further, a reflection preventing layer 5 is formed on the bottom surface of the groove part of the opening part by injecting ions from the opening part thereinto. Subsequently, a LOCOS oxidization is performed, and a silicon oxide film 6 is formed in the opening part. Then, after removing the silicon nitride film 3 by an anisotropic etching, the silicon oxide film 6 is removed to a predetermined depth, and the silicon substrate 1 to be changed into an active region 11 is exposed in a convex form. Thereafter, a gate oxide film 8 and a gate electrode part 9 are formed on the protruding substrate 1. Further, the protruding substrate 1 is subjected to an ion implantation, using the gate electrode part 9 as a mask, and it is annealed, and source/drain layers 10, 10 are formed out of it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and its manufacturing method.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional process for manufacturing a MOS transistor.

First, a silicon oxide film 2 having a thickness of about 600 Å is formed by thermal oxidation on the surface of a silicon substrate 1 doped to a desired conductivity type (P type), and then a film thickness is formed by a CVD method. A silicon nitride film 3 of about 1200Å is formed. After that, patterning is performed to open the silicon nitride film 3 and the silicon oxide film 2, and impurities (boron or the like) for preventing inversion are ion-implanted into the opening region to form an inversion prevention layer 5 (FIG. )).

Next, the film thickness is about 600 by locos oxidation.
An element isolation region 6 is formed of a 0Å silicon oxide film (FIG. 4B).

Next, after removing the silicon nitride film 3 and the silicon oxide film 2 to expose the surface of the silicon substrate 1,
A sacrificial oxide film 7 having a film thickness of about 300Å is formed, and ion implantation is performed for controlling the threshold voltage (FIG. 4C).

Next, after removing the sacrificial oxide film 7, a gate oxide film 8 having a film thickness of about 200 Å is formed, and an N ⁺ polysilicon film and a film having a film thickness of about 1500 Å to be a gate electrode material are formed on the entire surface. A tungsten silicide film having a thickness of about 2000Å is continuously formed and patterned to form the gate electrode portion 9 (FIG. 4D).

Next, using the gate electrode portion 9 as a mask, arsenic (As) or the like is implanted as an N-type impurity into a region to be the source / drain layer 10 and annealed to form the source / drain layer 10 (FIG. 4 (e)).

[0008]

The drive capability of a MOS transistor is almost determined by the gate length (L) and the gate width (W), and in order to obtain high drive capability, the gate length is made small and the gate width is made large. Just design. However, there is a problem of lowering the breakdown voltage and the problem of the short channel effect in order to reduce the gate length, and a problem of lowering the integration degree of the LSI in order to increase the gate width.

An object of the present invention is to provide a means for increasing the gate width without lowering the degree of integration of LSI.

[0010]

According to the field effect transistor of the present invention as set forth in claim 1, the active region has a convex cross section in a direction perpendicular to the source / drain direction, and has a gate electrode and a source / drain layer. Are provided on the upper surface and the side surface of the convex active region.

According to a second aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising a step of sequentially forming a silicon oxide film and a silicon nitride film on a semiconductor substrate, and after patterning, the silicon oxide film and the silicon oxide film. Etching the nitride film and the semiconductor substrate to form a groove portion having a predetermined depth and width at least in parallel to the source / drain direction at the edge of the region to be the active region on the semiconductor substrate; After performing ion implantation for preventing inversion, a step of forming an element isolation region in the groove by locos oxidation, and a step of removing the silicon nitride film, and then separating the element formed in the silicon oxide film and the groove Etching the region to a predetermined depth, exposing the semiconductor substrate surface portion in a convex shape, and the convex semiconductor substrate surface,
Having a step of forming a gate oxide film after performing ion implantation for controlling a threshold voltage, and a step of forming a gate electrode and a source / drain layer on an upper surface and a side surface of the convex semiconductor substrate. It is characterized by.

[0012]

By using the present invention, the gate width can be increased without lowering the degree of integration of the LSI.

[0013]

The present invention will be described in detail below based on an example.

FIG. 1 is a plan view of a MOS transistor according to an embodiment of the present invention, FIG. 2 is a manufacturing process diagram of the MOS transistor taken along the line AA 'in FIG. 1, and FIG.
FIG. 2 is a structural cross-sectional view of the transistor taken along the line BB ′ in FIG. 1.

As shown in FIG. 1, the MO of one embodiment of the present invention.
In the S transistor, the silicon substrate 1 around the active region 11 is removed, and an element isolation region 6 made of a silicon oxide film is formed in the region, and the silicon substrate 1 to be the active region has a convex shape as shown in FIGS. The gate electrode portion 9 and the source / drain layer 10 are formed on the upper surface and the side surface of the convex silicon substrate 1.

Next, the manufacturing process of the MOS transistor of one embodiment of the present invention will be described with reference to FIG.

First, the P-type doped silicon substrate 1 is thermally oxidized to form a silicon oxide film 2 having a thickness of about 600 Å, and then a silicon nitride film having a thickness of about 1200 Å is formed by a CVD method. 3 is formed (FIG. 2A).

Next, after applying a resist 4 on the entire surface, patterning is performed, and the silicon nitride film 3 and the silicon oxide film 2 are removed by anisotropic etching to remove the silicon substrate 1.
Is etched to a depth of about 3,000 Å, a region to be the element isolation region 6 is opened, and P ⁺ impurity such as boron is ion-implanted from the opening to form an inversion prevention layer 5 on the bottom surface of the groove. (FIG.2 (b)).

Next, locos oxidation is performed to obtain a film thickness of about 600.
A silicon oxide film 6 having a thickness of 0 Å is formed (FIG. 2C), and then the silicon nitride film 3 is removed by anisotropic etching, and then the silicon oxide film 6 is removed to a depth of about 3000 Å.
The silicon substrate 1 to be the active region 11 is exposed in a convex shape (FIG. 2D).

Next, a sacrificial oxide film 7 is formed to a film thickness of about 300Å, ions are implanted to control the threshold voltage of the MOS transistor (FIG. 2 (e)), and then the sacrificial oxide film 7 is formed.
Is removed and a gate oxide film 8 having a film thickness of about 200Å is formed by a thermal oxidation method, and becomes a gate electrode material on the entire surface. For example, an N ⁺ -type polysilicon film having a film thickness of about 1500Å and a film thickness of about A 2000 Å tungsten silicide film is formed and patterned to form the gate electrode portion 9 (FIG. 2).
(F)).

Next, using the gate electrode portion 9 as a mask, arsenic (As) or the like is implanted as an N-type impurity into the region to be the source / drain layer 10 (FIG. 2 (g)), and annealing is performed to form the source / drain. Forming the drain layer 10 (FIG. 2 (h)),
Complete the MOS transistor.

In this embodiment, the groove is provided around the active region. However, it is sufficient that the cross section of the active region in the direction perpendicular to the source / drain direction is convex, and the groove is formed around the entire active region. Need not be provided. Further, although the MOS transistor has been described in the present embodiment, the present invention is not limited to the MOS transistor and can be applied to any field effect transistor.

[0023]

As described above in detail, by using the present invention, by making the active region of the field effect transistor convex, the same two-dimensional field effect transistor as the conventional two-dimensional structure can be obtained. In a space, a larger gate width can be obtained, and in particular, the drive capability per unit length of a fine field effect transistor can be greatly improved.

Further, the increase of the threshold voltage (narrow channel effect) which occurs in the case of a fine gate width can be remarkably suppressed.

[Brief description of drawings]

FIG. 1 is a plan view of a MOS transistor according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the same MOS transistor.

FIG. 3 is a sectional view of the same MOS transistor.

FIG. 4 is a manufacturing process diagram of a conventional MOS transistor.

[Explanation of symbols]

 1 Silicon substrate 2 Silicon oxide film 3 Silicon nitride film 4 Resist 5 Inversion prevention layer 6 Element isolation region 7 Sacrificial oxide film 8 Gate oxide film 9 Gate electrode 10 Source / drain layer 11 Active region

Claims (2)

[Claims] 1. A cross section of the active region in a direction perpendicular to the source / drain direction has a convex shape, and a gate electrode and a source / drain layer are provided on an upper surface and a side surface of the convex active area. Characteristic field effect transistor. 2. A step of sequentially forming a silicon oxide film and a silicon nitride film on a semiconductor substrate, and after patterning, the silicon oxide film, the silicon nitride film and the semiconductor substrate are etched to be parallel to at least source / drain directions. A step of forming a groove portion having a predetermined depth and width at an edge portion of a region to be an active region on the semiconductor substrate; and after performing ion implantation for preventing inversion, the groove portion is formed by locos oxidation. A step of forming an element isolation region in, and after removing the silicon nitride film, etching the element isolation region formed in the silicon oxide film and the groove portion to a predetermined depth, the semiconductor substrate surface portion in a convex shape A step of exposing, a step of forming a gate oxide film after performing ion implantation for controlling a threshold voltage on the convex semiconductor substrate surface, Characterized in that the upper and side surfaces shaped for semiconductor substrate and a step of forming a gate electrode and source / drain layer, a method of manufacturing a field effect transistor.