JP2009117412A - Insulated gate semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulated gate semiconductor device which can avoid a process matter and bad influence to a device caused by high density of an impurity which is introduced for reducing resistance, reduce gate resistance, and thereby contribute to the improvement of a switching rate, and its manufacturing method. <P>SOLUTION: A gate electrode is formed by embedding a polysilicon layer in a trench and providing a conductor layer comprising a polycide layer on the upper surface of the polysilicon layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an insulated gate semiconductor device and a manufacturing method thereof, and more particularly, to an insulated gate semiconductor device having a trench structure for reducing gate resistance and a manufacturing method thereof.

  A conventional insulated gate semiconductor device will be described with reference to FIG. 9 by taking an n-channel MOSFET having a trench structure as an example.

  An n− type semiconductor layer 22 is provided on an n + type silicon semiconductor substrate 21 to form a drain region, and a p type channel layer 24 is provided on the surface thereof. A trench 27 penetrating the channel layer 24 and reaching the n − type semiconductor layer 22 is provided, an inner wall of the trench 27 is coated with a gate oxide film 28, and a gate electrode 32 made of polysilicon filled in the trench 27 is provided. An n + type source region 34 is formed on the surface of the channel layer 24 adjacent to the trench 27, and a p + type body region 33 is provided on the surface of the channel layer 24 between the source regions 34 of two adjacent cells. The gate electrode 32 is covered with an interlayer insulating film 35, and a source electrode 36 that contacts the source region 34 and the body region 33 is provided.

  With reference to FIG. 10, a method of manufacturing the MOSFET shown in FIG. 9 will be described.

  A substrate 20 in which an n− type semiconductor layer 22 is laminated on an n + type silicon semiconductor substrate 21 is prepared, and after an oxide film 23 is formed on the surface, the oxide film 23 in a predetermined channel layer 24 is etched. For example, boron is implanted into the entire surface using the oxide film 23 as a mask, and then diffused to form a p-type channel layer 24.

  Thereafter, the substrate 20 is dry-etched by using, for example, a mask obtained by patterning the CVD oxide film 25 into a desired shape, and a trench 27 penetrating the channel layer 24 and reaching the n − type semiconductor layer 22 is formed. A gate oxide film 28 is formed in the trench 27.

  Further, a non-doped polysilicon layer 29 is deposited on the entire surface, and phosphorus is implanted and diffused at a high concentration to increase the conductivity (FIG. 10A).

  The polysilicon layer 29 attached to the entire surface is dry-etched without providing a mask to form the gate electrode 32 embedded in the trench 27.

  A desired mask is provided on the surface of the channel layer 24 to introduce an n-type impurity for forming a source region and a p-type impurity for forming a body region, thereby forming an insulating film 35 'serving as an interlayer insulating film on the entire surface. By this heat treatment, n-type impurities and p-type impurities are diffused to form the source region 34 and the body region 33 (FIG. 10B).

The insulating film 35 'is patterned in a desired shape to form the interlayer insulating film 35, and the source electrode 36 is formed on the entire surface to obtain the final structure shown in FIG.
JP 2001-27497A

  In such a conventional MOSFET, the polysilicon buried in the trench is doped with high-concentration impurity ions to reduce the resistance of the gate electrode 32. However, the impurity concentration of the impurity to be doped has a limit.

  That is, if the impurity concentration is too high, the impurity ions in the gate electrode 32 ooze out from the gate oxide film 27 to the channel layer 24, causing a problem of adversely affecting the channel layer 24. In the case of a MOSFET, a protection diode may be formed on the chip for protection between the gate and the source. The protection diode is formed by patterning the same polysilicon layer as the gate electrode 32 in the same process. Therefore, if the impurity concentration doped in the polysilicon layer is too high, there is a problem that the breakdown voltage of the protective diode is deteriorated.

  On the other hand, with the miniaturization of the MOSFET cell, the width of the trench for embedding the polysilicon layer is narrowed, and the gate resistance tends to increase by adopting a stripe structure that facilitates further miniaturization. When the gate resistance increases, the delay of the CR time constant increases, and the switching (on / off) operation of each cell becomes non-uniform, so that breakdown due to current concentration is likely to occur.

  As described above, since there is a limit to the high concentration doping to the polysilicon layer, a method of forming a gate lead electrode and reducing the gate resistance is also known.

  FIG. 11 is a schematic view showing an example of a conventional gate lead electrode 38.

  The gate lead electrode 38 is formed of the same polysilicon layer as that of the gate electrode (not shown), and extends on the chip so as to surround the actual operation region E ′, which is a cell placement region. The electrode 39 is connected.

  However, if it is formed so as to be routed on the chip in order to reduce the resistance, the occupied area is increased accordingly, and the area as the cell arrangement region (actual operation region E ′) is affected. This is contrary to the purpose of proceeding and improving the cell density.

  The present invention has been made in view of such a problem. First, a one-conductivity-type semiconductor substrate, a one-conductivity-type semiconductor layer provided on the semiconductor substrate, and a reverse-conductivity-type semiconductor layer provided on the surface of the one-conductivity-type semiconductor layer. A channel layer, a trench penetrating the channel layer, a gate insulating film covering the inner wall of the trench, a polysilicon layer embedded in the trench, and a polysilicon layer provided on the surface of the polysilicon layer The problem is solved by providing a gate electrode made of a conductor layer having a low specific resistance and a source region of one conductivity type provided adjacent to the trench on the surface of the channel layer.

  Second, a step of preparing a substrate in which a one-conductivity-type semiconductor layer is stacked on a one-conductivity-type semiconductor substrate and forming a reverse-conductivity-type channel layer on the surface of the semiconductor layer; A step of forming a trench reaching up to, a step of forming a gate insulating film on the inner wall of the trench, a polysilicon layer embedded in the trench, and a resistivity formed from the polysilicon layer formed on the surface of the polysilicon layer And a step of forming a one-conductivity type source region adjacent to the trench on the surface of the channel layer.

  According to the present invention, the following effects can be obtained.

  According to the structure of the present invention, since the gate electrode is constituted by the polysilicon layer, the polycide layer, and the metal layer, the gate resistance can be reduced while maintaining the impurity concentration of the polysilicon layer as usual. Specifically, since the specific resistance of the polycide layer is lower than that of the polysilicon layer of the gate electrode (the specific resistance of the polycide layer is one half of the specific resistance of the polysilicon layer), the impurity of the gate electrode is highly concentrated. The gate resistance can be reduced by avoiding the influence on the device.

  Further, the delay of the CR time constant can be reduced by reducing the gate resistance. In particular, in this embodiment, the resistance of the gate electrode is reduced for each cell, the non-uniformity of the switching operation of each cell is reduced, and the occurrence of breakdown due to current concentration can be prevented.

  Further, the area occupied by the polysilicon layer (gate lead electrode) drawn on the substrate can be reduced. That is, the area of the operation region can be increased correspondingly, and the gate resistance can be reduced.

  Further, since the polycide layer can be formed by self-alignment on the polysilicon layer constituting the gate electrode by depositing metal on the entire surface and performing heat treatment, the gate resistance can be reduced without complicating the manufacturing process.

  Furthermore, the polycide layer can be formed on the gate lead electrode by self-alignment.

  An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 8 by taking an n-channel type MOSFET having a trench structure as an example.

  1A and 1B are diagrams for explaining a MOSFET according to the present embodiment. FIG. 1A is a cross-sectional view, FIG. 1B is a schematic diagram of a plane of the present embodiment, and FIG. 11 is a schematic diagram of a conventional plane. FIG.

  Referring to FIG. 1A, MOSFET 100 includes a one-conductivity type semiconductor substrate 1, a one-conductivity type semiconductor layer 2, a reverse-conductivity type channel layer 4, a trench 7, a gate insulating film 11, a gate, An electrode 13 and a source region 15 are included.

  In the substrate 10, an n− type semiconductor layer (for example, an epitaxial layer) 2 is stacked on an n + type silicon semiconductor substrate 1 to form a drain region.

  The channel layer 4 is a p-type impurity region provided on the surface of the n − type semiconductor layer 2. The trench 7 is provided at a depth that reaches the n − type semiconductor layer 2 through the channel layer 4, and covers the inner wall of the trench 7 with a gate insulating film (oxide film) 11 having a thickness corresponding to the driving voltage. .

A gate electrode 13 is embedded in the trench 7. The gate electrode 13 includes a polysilicon layer 13a doped with impurities (for example, phosphorus (P)) (impurity concentration of about 1E19 cm ⁻³ ) and a conductor layer 13b provided on the surface of the polysilicon layer 13a. The conductor layer 13b is a polycide layer.

  More specifically, the polysilicon layer 13a is buried at a height from the opening of the trench 7 to, for example, about 2000 mm below. The conductor layer 13b on the polysilicon layer 13a is about 2000 mm. The conductor layer 13b is a polycide layer obtained by heat-treating a refractory metal layer (for example, tungsten (W), molybdenum (Mo), etc.) provided on the polysilicon layer 13a.

  The conductor layer 13b has substantially the same thickness near the side wall of the trench 7 and near the center. Further, in the trench 7, it is provided only on the upper surface of the polysilicon layer 13a. That is, only the conductor layer 13b is embedded in the trench 7 with a thickness of about 2000 mm from the opening, and only the polysilicon layer 13a is embedded below the conductor layer 13b. The conductor layer 13b is completely embedded in the trench 7.

  A source region 15 that is a high-concentration n-type impurity region is provided on the surface of the channel layer 4 adjacent to the trench 7, and a body that is a high-concentration p-type impurity region is formed on the surface of the channel layer 4 between the adjacent source regions 15. Region 14 is provided. Source region 15 is adjacent to gate electrode 13 through gate oxide film 11. A region surrounded by the trench 7 is one cell of the MOSFET.

  The interlayer insulating film 16 covers at least the gate electrode 13 and covers the opening of the trench 7.

  The source electrode 17 is made of Al or the like and is generally a wiring layer that contains silicon to prevent spikes and is patterned into a desired wiring shape. The source electrode 17 is connected via a contact hole CH between the interlayer insulating films 16. The region 15 and the body region 14 are contacted.

  In the present embodiment, the gate electrode 13 embedded in the trench 7 is constituted by a polysilicon layer 13a and a conductor layer 13b provided on the upper surface thereof.

  The specific resistance of the conductor layer 13b (polycide layer) is half of the specific resistance of the polysilicon layer 13a. Therefore, the gate resistance can be reduced as compared with the case where the gate electrode 13 is formed only of the polysilicon layer.

  Further, although the delay of the CR time constant can be avoided as a whole chip, in particular, since the gate resistance can be uniformly reduced for each gate electrode 13, the switching (on / off) operation of each cell can be made uniform, and due to current concentration. The occurrence of destruction can be suppressed.

  FIG. 1B is a plan view showing an outline of the gate lead electrode provided in the peripheral portion of the MOSFET.

  The gate lead electrode 18 is connected to the gate electrode 13 formed in the trench 7, extends so as to lead the gate electrode 13 to the surface of the substrate 10, and is connected to the gate pad electrode 19. The gate lead electrode 18 has the same configuration as the gate electrode 13. That is, it is composed of a polysilicon layer 13a and a conductor layer 13b overlapping therewith. Note that a gate wiring made of a metal layer overlapping therewith is provided on the gate lead electrode 18, but illustration thereof is omitted here.

  That is, according to the present embodiment, since the resistance can be reduced also in the gate lead electrode 18, for example, the width W of the gate lead electrode 18 can be made narrower than in the prior art. Further, when the gate electrode 13 (trench 7) is patterned in a lattice pattern, the gate lead electrode 18 can be formed as a part instead of the entire periphery of the chip as shown in FIG.

  The conventional gate lead electrode 38 is provided at the entire periphery of the chip and in the middle of the chip and connected to the gate pad electrode 39 in order to reduce the resistance by securing the length thereof. For this reason, there is a limit to the increase in the area of the actual operation region E ′ where the MOSFET cells are arranged (FIG. 11).

  However, according to the present embodiment, since the resistance of the gate lead electrode 18 can be reduced, it can be partially arranged, and the area of the actual operation region E can be increased correspondingly.

  A method of manufacturing the MOSFET shown in FIG. 1 will be described with reference to FIGS.

  The method for manufacturing a MOSFET according to the present embodiment includes a step of preparing a substrate in which a one-conductivity-type semiconductor layer is stacked on a one-conductivity-type semiconductor substrate, and forming a reverse-conductivity-type channel layer on the surface of the semiconductor layer; Forming a trench that passes through the semiconductor layer and reaching the semiconductor layer, forming a gate insulating film on the inner wall of the trench, a polysilicon layer embedded in the trench, and formed on the surface of the polysilicon layer, The method includes a step of forming a gate electrode made of a conductor layer having a specific resistance lower than that of a polysilicon layer, and a step of forming a source region of one conductivity type adjacent to the trench on the surface of the channel layer.

  1st process (refer FIG. 2): The process of preparing the board | substrate which laminated | stacked one conductivity type semiconductor layer on the semiconductor substrate of one conductivity type, and forming a channel layer of a reverse conductivity type on the semiconductor layer surface.

A substrate 10 in which a drain region is formed by laminating an n− type semiconductor layer (for example, an epitaxial layer) 2 on an n + type silicon semiconductor substrate 1 is prepared. After an oxide film (not shown) is formed on the surface of the substrate 10 (n− type semiconductor layer 2), the oxide film in the region where the channel layer is to be formed is etched. A predetermined p-type impurity (for example, boron) is implanted into the entire surface using this oxide film as a mask (dose amount: about 1E13 cm ⁻² ), and then diffused to form the channel layer 4.

  Second step (see FIG. 3): a step of forming a trench that penetrates the channel layer and reaches the semiconductor layer.

  An NSG (Non-doped Silicate Glass) CVD oxide film 5 is formed on the entire surface by CVD, a resist mask PR for trench formation is provided, the CVD oxide film 5 is partially removed by dry etching, and a channel region A trench opening OP in which 4 is exposed is formed (FIG. 3A).

  Further, using the CVD oxide film 5 as a mask, the substrate 10 in the trench opening OP is dry-etched with CF-based gas and HBr-based gas to form a trench 7 that penetrates the channel layer 4 and reaches the n − -type semiconductor layer 2 (FIG. 3 (B)).

  Third step (see FIG. 4): a step of forming a gate insulating film on the inner wall of the trench.

  Dummy oxidation is performed to form a dummy oxide film (not shown) on the inner wall of the trench 7 and the surface of the channel layer 4 to remove etching damage during dry etching. The dummy oxide film and the CVD oxide film formed by this dummy oxidation are simultaneously removed by an oxide film etchant such as hydrofluoric acid. Thereby, a stable gate oxide film can be formed. In addition, the thermal oxidation at a high temperature has an effect of rounding the opening of the trench 7 to avoid electric field concentration at the opening of the trench 7. Thereafter, a gate oxide film 11 is formed. That is, the entire surface is thermally oxidized to form the gate oxide film 11 with a film thickness of several hundreds of squares according to the threshold value.

  Fourth step (see FIGS. 5 and 6): a step of forming a gate electrode comprising a polysilicon layer embedded in the trench and a conductor layer formed on the surface of the polysilicon layer and having a specific resistance lower than that of the polysilicon layer.

  First, referring to FIG. 5, a polysilicon layer is buried in the trench 7.

A non-doped polysilicon layer 13a is deposited on the entire surface, and phosphorus or the like (impurity concentration: about 1E19 cm ⁻³ ) is implanted and diffused to increase the conductivity. Alternatively, a polysilicon layer 13a doped with an impurity such as phosphorus in advance may be deposited (FIG. 5A).

  The polysilicon layer 13 deposited on the entire surface is dry-etched without a mask to bury the polysilicon layer 13 a in the trench 7. The polysilicon layer 13a is located about 1000 mm below the opening of the trench 7, for example.

  Next, referring to FIG. 6, a conductor layer 13b is formed on polysilicon layer 13a.

  That is, a refractory metal layer 13b 'such as tungsten (W) or titanium (Ti) is deposited on the entire surface. The thickness of the refractory metal layer 13b 'is, for example, about 2000 mm (FIG. 6A).

  Thereafter, heat treatment (for example, 1000 ° C., 30 minutes) is performed. As a result, the polysilicon layer 13a and the refractory metal layer 13b 'react to form a polycide layer (conductor layer) 13b on these contact surfaces. The thickness of the polycide layer 13b is, for example, about 2000 mm (FIG. 6B).

  Next, the refractory metal layer 13b 'on the polycide layer 13b is removed by wet etching without providing a mask.

  Thereby, the polysilicon layer 13a and the conductor layer (polycide layer 13b) overlapping therewith are formed by self-alignment. The polycide layer becomes a conductor layer 13b having a specific resistance lower than that of the polysilicon layer 13a. The conductor layer 13b is completely buried in the trench 7 and formed only on the upper surface of the polysilicon layer 13a, and the gate electrode 13 is formed by the polysilicon layer 13a and the conductor layer 13b (FIG. 6C). ).

  Although illustration is omitted here, the gate electrode 13 in the trench 7 is drawn onto the substrate 10 outside the region (actual operation region) where the transistor cells are arranged to become the gate lead electrode 18, and the gate pad. Connected to the electrode 19 (see FIG. 1B). That is, the polycide layer 13b is formed in the formation region of the polysilicon layer 13a so as to overlap (with the same pattern) other than that shown in FIG.

  Thus, in the present embodiment, the conductor layer (polycide layer) 13b having a specific resistance lower than that of the polysilicon layer 13a is formed on the polysilicon layer 13a constituting the gate electrode 13. The conductor layer 13b can be formed on the polysilicon layer 13a by self-alignment.

  Fifth step (see FIG. 7): a step of forming a source region of one conductivity type adjacent to the trench on the surface of the channel layer.

  First, impurities such as boron are selectively ion-implanted with a resist mask (not shown) to form a p + -type impurity region 14a, and the resist mask is removed. Further, a new resist mask (not shown) is used to mask the planned source region 15 and gate electrode 13, and an impurity such as arsenic is ion-implanted to form an n + -type impurity region 15a. Remove. Note that after the n-type impurity is ion-implanted, the p-type impurity may be ion-implanted (FIG. 7A).

  Thereafter, a BPSG (Boron Phosphorus Silicate Glass) layer 16a is deposited on the entire surface by the CVD method, p-type and n-type impurities are diffused on the substrate surface, and an n + type source region 15 is formed on the surface of the channel layer 4 adjacent to the trench 7. And p-type body region 14 is formed on the substrate surface between adjacent source regions 15 (FIG. 7B).

  Sixth step (see FIG. 8): a step of forming an interlayer insulating film covering the gate electrode.

  The BPSG film 16 a is etched with a resist mask, leaving the interlayer insulating film 16 on at least the gate electrode 13. The interlayer insulating film 16 covers the opening of the trench 7 and is provided with a thickness of about 8000 mm, for example.

  Thereafter, a metal layer (for example, an Al / Si layer) is sputtered on the entire surface. The film thickness is, for example, about 2 μm. The metal layer is patterned into a desired wiring shape, and the source electrode 17 is formed. Although illustration is omitted here, the gate wiring and the gate pad electrode connected to the gate electrode 13 and overlapping the gate lead-out electrode are also formed by patterning of the same metal layer.

  In the present embodiment, an n-channel MOSFET has been described as an example. However, the present invention is not limited to this, and a p-channel MOSFET having a reversed conductivity type may be used, and the present invention can be similarly applied to an insulated gate transistor such as an IGBT.

It is (A) sectional drawing and (B) top view explaining the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the conventional insulated gate semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional insulated gate semiconductor device. It is a top view explaining the conventional insulated gate semiconductor device.

Explanation of symbols

1 n + type silicon semiconductor substrate
2 n-type semiconductor layer
4 channel layer
7 Trench
10 Substrate
11 Gate oxide film
13 Gate electrode
13a Polysilicon layer
13b Conductor layer (polycide layer)
13 'refractory metal layer
14 Body region
15 Source region
16 Interlayer insulation film
17 Source electrode
18 Gate lead electrode
19 Gate pad electrode
21 n + type silicon semiconductor substrate
22 n-type semiconductor layer
23 Oxide film
24 channel layer
27 Trench
28 Gate oxide film
32 Gate electrode
33 Body area
34 Source area
35 Interlayer insulation film
36 Source electrode
38 Gate extraction electrode
39 Gate pad electrode
100 MOSFET

Claims (9)

A semiconductor substrate of one conductivity type;
One conductivity type semiconductor layer provided on the semiconductor substrate;
A reverse conductivity type channel layer provided on the surface of the one conductivity type semiconductor layer;
A trench penetrating the channel layer;
A gate insulating film covering the inner wall of the trench;
A polysilicon layer embedded in the trench, and a gate electrode formed on a surface of the polysilicon layer and made of a conductor layer having a specific resistance lower than that of the polysilicon layer;
A source region of one conductivity type provided adjacent to the trench on the surface of the channel layer;
An insulated gate semiconductor device comprising:   The insulated gate semiconductor device according to claim 1, wherein the conductor layer is a polycide layer.   The insulated gate semiconductor device according to claim 1, wherein the conductor layer is embedded in the trench.   2. The insulated gate semiconductor device according to claim 1, wherein the conductor layer is provided only on an upper surface of the polysilicon layer.   2. The insulated gate semiconductor device according to claim 1, further comprising a gate lead electrode connected to the gate electrode and extending on the semiconductor layer, wherein the conductor layer is provided on the gate lead electrode. . Preparing a substrate in which a one-conductivity-type semiconductor layer is stacked on a one-conductivity-type semiconductor substrate, and forming a reverse-conductivity-type channel layer on the semiconductor layer surface;
Forming a trench that penetrates the channel layer and reaches the semiconductor layer;
Forming a gate insulating film on the inner wall of the trench;
Forming a gate electrode comprising a polysilicon layer embedded in the trench and a conductor layer formed on the surface of the polysilicon layer and having a lower specific resistance than the polysilicon layer;
Forming a source region of one conductivity type adjacent to the trench on the surface of the channel layer;
A method of manufacturing an insulated gate semiconductor device, comprising:   The gate electrode is formed by embedding the polysilicon layer in the trench, depositing a refractory metal layer on the entire surface, forming the conductor layer as a polycide layer by heat treatment, and embedding the conductor layer in the trench. The method of manufacturing an insulated gate semiconductor device according to claim 6, wherein the method is formed by patterning.   The method of manufacturing an insulated gate semiconductor device according to claim 6, wherein the conductor layer is formed only on an upper surface of the polysilicon layer.   The insulated gate semiconductor according to claim 6, wherein a gate lead electrode connected to the gate electrode and extending on the semiconductor layer is formed, and the conductor layer is formed on the gate lead electrode. Device manufacturing method.

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