JPH1126584A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, having a trench isolation structure and a method for manufacturing the device which simultaneously increase the yield and integration. SOLUTION: At least the inner side surfaces in the openings of trenches 32 are covered with an SiN film 42 having an etching characteristic different from that of an SiO2 film 44 as an interlayer insulating film. Accordingly, even if a connection hole 45 extends on an isolation region, exposure of the side surfaces of an Si substrate 31 facing the trenches 32 can be prevented when forming a connection hole 45. Further, occurrence of leak current between wiring formed in the connection hole 45 and a well 34 can be prevented. Further, the area of a diffusion layer 43 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a trench element isolation structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional MIS transistor having a trench element isolation structure and having a source / drain connection hole formed in self-alignment with a gate electrode. In this conventional MIS transistor, a trench 1 for element isolation is formed in a Si substrate 11.
2 are provided, and the trench 12 is formed of the SiO ₂ film 1
Filled with three.

A well 14 is provided in the Si substrate 11, and a gate insulating film made of an SiO ₂ film 15 or the like is provided on the surface of the element active region. SiO ₂ film 15, 1
A gate electrode made of a polycrystalline Si film 16 or the like is provided on 3 or the like, and a SiN film 17 as an offset insulating film is laminated on the polycrystalline Si film 16.

A low-concentration diffusion layer 21 is provided in the device active region on both sides of the polycrystalline Si film 16 and the SiN film 17, and a Si layer is formed on the side surfaces of the polycrystalline Si film 16 and the SiN film 17.
A sidewall protection film made of an N film 22 is provided. SiN
A high concentration diffusion layer 23 is provided in an element active region surrounded by the film 22 and the SiO ₂ film 13.
The source / drain of the LDD structure is constituted by 1, 23.

[0005] An interlayer insulating film made of a SiO ₂ film 24 is provided on the Si substrate 11, and the removal speed of SiN is S
The SiO ₂ film 24 is etched under conditions slower than the removal rate of iO ₂ , and a connection hole 25 for the diffusion layer 23 is formed in a self-aligned manner with the polycrystalline Si film 16.

That is, the position of the connection hole 25 with respect to the diffusion layer 23 is displaced due to misalignment of a mask in lithography for forming the connection hole 25, and the SiN film 22 serving as a sidewall protection film and the SiN film serving as an offset insulating film Even if the connection hole 25 spreads over the film 17, these SiN
The etching of the films 22 and 17 is suppressed, and the polycrystalline Si film 16 is not exposed. Therefore, the wiring (not shown) formed in the connection hole 25 and the polycrystalline Si film 1 serving as the gate electrode are formed.
6 is prevented.

[0007]

However, as described above, the position of the connection hole 25 with respect to the diffusion layer 23 is shifted, and
When 5 extends to over the trench 12, since there is no difference in removal rates in the SiO ₂ film 24 is a SiO ₂ film 13 and the interlayer insulating film that fills the trench 12, SiO ₂ at the time of forming the connecting hole 25 The SiO ₂ film 13 is also etched by the over-etching of the
The concave portion 26 exposing the inner surface on the side of the diffusion layer 23 is made of SiO.
_Two films 13 are formed.

When the deep recess 26 is formed, not only the side surface of the diffusion layer 23 but also the side surface of the well 14 are exposed. For this reason, even if the diffusion layer 23 and the well 14 are reverse-biased, a leak current occurs between the wiring formed in the connection hole 25 and the well 14, so that the yield is reduced.

Therefore, conventionally, the area of the diffusion layer 23 has been increased so that the connection hole 25 does not spread over the trench 12 even if the position of the connection hole 25 with respect to the diffusion layer 23 is shifted. However, when the area of the diffusion layer 23 is increased in this way,
The integration degree of the MIS transistor cannot be increased.

In other words, conventionally, it is possible to simultaneously prevent the occurrence of a leak current between the wiring formed in the connection hole 25 and the well 14 to increase the yield and to increase the degree of integration at the same time. I couldn't do that. Therefore,
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a trench element isolation structure and a method for manufacturing the same, which can simultaneously increase both the yield and the degree of integration.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device in which a trench for element isolation is provided in a semiconductor substrate and an interlayer insulating film is provided on the semiconductor substrate. It is characterized in that at least the inner side surface at the opening of the trench is covered with an insulating film having different etching characteristics from the interlayer insulating film.

In the semiconductor device according to the first aspect, since the etching characteristics of the insulating film and the interlayer insulating film covering the inner side surface of the opening of the trench for element isolation are different from each other, the connection hole for the semiconductor substrate is formed by the interlayer insulating film. If the etching is performed under the condition that the removal rate of the insulating film is lower than the removal rate of the interlayer insulating film when forming the film, even if the position of the connection hole is shifted and the connection hole spreads over the element isolation region, the trench is formed. The exposure of the side surface of the semiconductor substrate facing the substrate can be prevented.

A semiconductor device according to a second aspect of the present invention is characterized in that a sidewall protective film made of the same insulating film as the insulating film is provided on a side surface of the wiring on the semiconductor substrate.

In the semiconductor device according to the present invention, since the side wall protective film made of an insulating film having an etching characteristic different from that of the interlayer insulating film is provided on the side surface of the wiring, the removing speed of the insulating film is reduced. If the etching is performed under a condition lower than the speed, a connection hole can be formed in a self-aligned manner with respect to the wiring.

In addition, since the insulating film covering the inner side surface of the opening of the element isolation trench and the insulating film serving as the side wall protective film of the wiring are the same layer, these insulating films can be simultaneously formed and formed. Can be processed. For this reason,
Forming a connection hole in a self-aligned manner with respect to a wiring and preventing exposure of a side surface of a semiconductor substrate facing a trench by simply adding a step for lowering an opening of a trench below a surface of a semiconductor substrate. And both can be realized.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
A trench for element isolation is provided in the semiconductor substrate,
In a method of manufacturing a semiconductor device, wherein an interlayer insulating film is provided on the semiconductor substrate and on wiring on the semiconductor substrate, a step of forming the trench having an opening lower than a surface of the semiconductor substrate; A step of covering the wiring and the trench with an insulating film having an etching characteristic different from that of an insulating film; and forming the sidewall protective film made of the insulating film on a side surface of the wiring by etching the insulating film anisotropically. Leaving the insulating film covering at least the inner side surface of the opening in the trench.

In the method of manufacturing a semiconductor device according to the third aspect, since the sidewall protective film made of an insulating film having an etching characteristic different from that of the interlayer insulating film is formed on the side surface of the wiring, the connection hole for the semiconductor substrate is formed in the interlayer insulating film. At the time of formation, if etching is performed under the condition that the removal rate of the insulating film is lower than the removal rate of the interlayer insulating film, a connection hole can be formed in a self-aligned manner with respect to the wiring.

Further, since the inner surface at the opening of the trench for element isolation is covered with an insulating film having an etching characteristic different from that of the interlayer insulating film, when the connection hole for the semiconductor substrate is formed in the interlayer insulating film, If etching is performed under the condition that the removal speed is lower than the removal speed of the interlayer insulating film, even if the position of the connection hole is shifted and the connection hole spreads over the element isolation region, exposure of the side surface of the semiconductor substrate facing the trench is prevented. can do.

In addition, by simultaneously etching the same layer of insulating film, an insulating film serving as a sidewall protection film for the wiring and an insulating film covering the inner side surface of the opening of the trench for element isolation are formed. Only forms a trench lower than the surface of the semiconductor substrate and realizes both the formation of the connection hole in a self-aligned manner with respect to the wiring and the prevention of the exposure of the side surface of the semiconductor substrate facing the trench. Can be.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An MIS transistor having a trench element isolation structure and having a source / drain connection hole formed in a self-aligned manner with a gate electrode and a method of manufacturing the same will be described below. An embodiment of the present invention will be described with reference to FIGS.

In order to manufacture the MIS transistor of this embodiment, as shown in FIG. 2A, an SiN film (not shown) is formed on a Si substrate 31, and an element isolation penetrating the SiN film is formed. Trench 32 is formed in Si substrate 31. Then, depositing a SiO ₂ film 33 on the entire surface of the Si substrate 31 including the trenches 32, a trench a SiO ₂ film 33 by chemical mechanical polishing in which the SiN film as a stopper 32
Leave only within.

Thereafter, the SiN film is removed and the Si substrate 31 is removed.
After the well 34 is formed, Si as a gate insulating film is formed.
An O ₂ film 35 and the like are formed on the surface of the element active region. Then, the polycrystalline Si film 36 and Si as an offset insulating film are formed.
An N film 37 is sequentially deposited on the SiO ₂ films 35 and 33, and the SiN film 37 and the polycrystalline Si film 36 are etched using the resist 38 of the gate electrode pattern as a mask.

Next, as shown in FIG.
The SiO ₂ films 33 and 35 are anisotropically etched by RIE while leaving 8, so that the surface of the SiO ₂ film 33 in the trench 32 is lower than the surface of the Si substrate 31.

Next, as shown in FIG.
8 is removed and impurities are ion-implanted using the SiN film 37 and the SiO ₂ film 33 as a mask to form a polycrystalline Si film 36.
Then, a low-concentration diffusion layer 41 for source / drain having an LDD structure is formed in the element active region on both sides of the SiN film 37.
Then, an SiN film 42 is deposited on the entire surface of the Si substrate 31 including the inside of the trench 32 by the CVD method.

Next, as shown in FIG.
The entire surface of the iN film 42 is anisotropically etched to form a polycrystalline S
At the same time as forming the sidewall protection film made of the SiN film on the side surfaces of the i film and the SiN film 37, the trench 32 above the SiO ₂ film 33 is filled with the sidewall protection film made of the SiN film. That is, the inside of the trench 32 is filled with the SiO ₂ film 33, and the trench 32 above the SiO ₂ film 33 is filled.
Is filled with a SiN film 42.

Next, as shown in FIG.
Impurity ion implantation using masks 7 and 42 as a mask
In the element active region surrounded by the SiN film 42, a high concentration diffusion layer 43 for source / drain having an LDD structure is formed. Then, as shown in FIG. 3C, an SiO ₂ film 44 is deposited on the Si substrate 31 by a CVD method to form an interlayer insulating film.

Next, a resist (not shown) having an opening of a connection hole pattern for the diffusion layer 43 is formed on the SiO ₂ film 44 by lithography, and using this resist as a mask, as shown in FIG. SiO _{2 by} RIE under the following conditions
The connection hole 45 is formed by anisotropically etching the film 44.

RIE conditions for forming connection holes Gas: C ₄ F ₈ / CO / Ar = 10/200 / 200s
ccm Pressure: 5Pa High frequency power: 1600W

Under the above RIE conditions, the removal rate of SiN is lower than the removal rate of SiO ₂ , so that the connection hole 45 for the diffusion layer 43 is self-aligned with both the polycrystalline Si film 36 and the element isolation region. It is formed. That is, even if the position of the connection hole 45 is shifted and the connection hole 45 spreads over the polycrystalline Si film 36 and the element isolation region, the SiN films 37 and 42
Is suppressed, so that not only the polycrystalline Si film 36 but also the SiO ₂ film 33 are not exposed.

For this reason, unlike the conventional example shown in FIG. 4, a recess for exposing the inner surface of the trench 32 on the diffusion layer 43 side is not formed in the SiN film 42 in the trench 32, but in the connection hole 45. A short circuit between the formed wiring (not shown) and the well 34 is prevented.

In the above embodiment, the SiO ₂ film in the trench 32 is formed after the SiN film 37 and the polycrystalline Si film 36 are etched into the pattern of the gate electrode and before the low concentration diffusion layer 41 is formed. 33, the SiO ₂ film 33 is etched by the SiN film 37.
After the polycrystalline Si film 36 is etched into the pattern of the gate electrode and before the deposition of the SiN film 42, it may be performed at any time, for example, after the low concentration diffusion layer 41 is formed.

The SiN film 37 and the polycrystalline Si film 36
The etching of the SiO ₂ film 33 in the trench 32 after etching the gate electrode pattern is performed by etching and depositing the polycrystalline Si film 36 and the like after etching the SiO ₂ film 33 in the trench 32. This is because a step is formed in the polycrystalline Si film 36 at the boundary between the element 32 and the element active region, and electric field concentration occurs in this step, causing anomalies in characteristics due to the narrow channel effect and the like.

In the above embodiment, the trench 32
Is filled with the SiO ₂ film 33 and only the opening of the trench 32 above the SiO ₂ film 33 is filled with the SiN film 42. However, the entire trench 32 may be filled with the SiN film 42. After forming an insulating film on the inner surface of the trench 32 by a CVD method, a thermal oxidation method, or the like, the trench 32 may be filled with a conductive film such as a polycrystalline Si film or an insulating film.

Further, in the above embodiment, the trench 32
Is filled with the SiN film 42, but the entire surface of the opening of the trench 32 does not necessarily need to be filled with the SiN film 42, and at least the inner side surface of the opening of the trench 32 is made of the SiN film 42. What is necessary is just to be covered with the side wall protective film. In the above embodiments, the invention of the present application is applied to a MIS transistor and a method of manufacturing the same. However, the invention of the present application can be applied to a semiconductor device other than the MIS transistor and a method of manufacturing the same.

[0035]

In the semiconductor device according to the first aspect, even if the position of the connection hole with respect to the semiconductor substrate is shifted and the connection hole is extended to the element isolation region, the side surface of the semiconductor substrate facing the isolation trench is exposed. Therefore, it is possible to prevent the occurrence of a leak current between the wiring formed in the connection hole and the semiconductor substrate, and it is possible to increase the yield.

As described above, even if the connection hole for the semiconductor substrate extends over the element isolation region, it is possible to prevent the occurrence of a leakage current between the wiring formed in the connection hole and the semiconductor substrate. Therefore, the area of the semiconductor substrate to be connected to the wiring formed in the connection hole can be reduced, and the degree of integration can be increased.

In the semiconductor device according to the second aspect, the connection hole is formed in a self-aligned manner with respect to the wiring by merely adding a step for lowering the opening of the trench below the surface of the semiconductor substrate. To prevent the exposure of the side surface of the semiconductor substrate facing the
It is possible to achieve an improvement in yield and a further increase in integration while suppressing an increase in manufacturing cost.

In the method of manufacturing a semiconductor device according to the third aspect, only by forming a trench whose opening is lower than the surface of the semiconductor substrate, the connection hole is formed in a self-aligned manner with respect to the wiring and faces the trench. Since it is possible to both prevent exposure of the side surface of the semiconductor substrate, it is possible to manufacture a semiconductor device having a high degree of integration and a high yield while suppressing an increase in manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a side sectional view of a MIS transistor as one embodiment of the present invention.

FIG. 2 is a side sectional view showing the first half of a method for manufacturing a MIS transistor as one embodiment in the order of steps;

FIG. 3 is a side sectional view showing the latter half of the method of manufacturing the MIS transistor as one embodiment in the order of steps;

FIG. 4 is a side sectional view of a MIS transistor as a conventional example of the present invention.

[Explanation of symbols]

31: Si substrate (semiconductor substrate), 32: trench, 36
... polycrystalline Si film (wiring), 42 ... SiN film (insulating film)
44: SiO ₂ film (interlayer insulating film)

Claims (3)

[Claims] In a semiconductor device having a trench for element isolation provided in a semiconductor substrate and an interlayer insulating film provided on the semiconductor substrate, at least an insulating film having an etching characteristic different from that of the interlayer insulating film. A semiconductor device, wherein an inner side surface of an opening of the trench is covered. 2. The semiconductor device according to claim 1, wherein a side wall protective film made of the same insulating film as the insulating film is provided on a side surface of the wiring on the semiconductor substrate. 3. The method of manufacturing a semiconductor device, wherein a trench for element isolation is provided in a semiconductor substrate, and an interlayer insulating film is provided on the semiconductor substrate and on wiring on the semiconductor substrate. Forming the trench lower than the surface of the semiconductor substrate, covering the wiring and the trench with an insulating film having an etching characteristic different from that of the interlayer insulating film, and etching the insulating film anisotropically. Forming a sidewall protective film made of the insulating film on the side surface of the wiring and leaving the insulating film covering at least the inner side surface of the opening in the trench. Manufacturing method.