JP2745970B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation region in a semiconductor device.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated, M
As device dimensions such as the gate dimension of the OS transistor and the width of the aluminum wiring are reduced, the importance of reducing the width of the element isolation region is also increasing. Conventionally, as a device isolation technology in a MOS device having a high device density,
Groove separation is well known. A method for suppressing the leakage current at the groove side wall is described in Japanese Patent Application Laid-Open No. 2-304926.

Referring to FIGS. 3 and 4 which are cross-sectional views in the order of steps for explaining a method of manufacturing a semiconductor device, the outline of the method described in the above publication is as follows. First,
The surface of the P-type silicon substrate 1 is thermally oxidized to form a silicon oxide film 12, and a photoresist 6a covering a region other than a region where an element isolation region is formed [FIG.
(A)]. Next, the silicon oxide film 12 is etched using the photoresist 6a as a mask to form an opening. After removing the photoresist 12 and depositing the CVD silicon film 14 on the entire surface, for example, 30 keV, 1.0 ×
By ion implantation of boron at 10 ¹³ cm ^-2 , a P ⁺ diffusion layer 7c is formed on the surface of the P-type silicon substrate 1 exposed at the opening.
Is formed (FIG. 3B).

Next, a CVD silicon film 15 is deposited on the entire surface again (FIG. 3C). By the anisotropic etching of silicon, the CVD silicon film 14a,
Then, a spacer made of the CVD silicon film 15a is formed. Next, the silicon oxide film 12, the CVD silicon film 1
4a and the CVD silicon film 15a as a mask.
Anisotropic etching of the silicon substrate 1 is performed to form a groove 9a that penetrates the P ⁺ diffusion layer 7c and is self-aligned with the spacer. Boron ions are implanted at an incident angle perpendicular to the surface of the P-type silicon substrate 1 to form a P ⁺ diffusion layer 7d at the bottom of the groove 9a (FIG. 4A).

Next, the silicon oxide film 12, the CVD silicon film 14a, and the CVD silicon film 15a are removed by etching. Thereafter, a silicon oxide film 16 is again formed by thermal oxidation on the surface of the P-type silicon substrate 1 including the surface of the groove 9a, and a CV film having a thickness of at least half the width of the groove 9a is formed.
A D silicon nitride film 17 is deposited to fill the inside of the trench 9a, and a CVD silicon oxide film 18 is further deposited on the entire surface (FIG. 4B). Next, a photoresist 6b covering a region where the element isolation region is formed is formed. Using the photoresist 6b as a mask, the CVD silicon oxide film 18, the CVD silicon nitride film 17, and the silicon oxide film 16 are sequentially etched to form the CVD silicon oxide film 1
8a, a CVD silicon nitride film 17a, and a silicon oxide film 16a are formed. [FIG. 4 (c)]. By removing the photoresist 6b, a semiconductor device having an element isolation region described in the above publication can be obtained.

[0006]

In the method of forming an element isolation region described in the above publication, the CVD silicon oxide film 18a,
CVD silicon nitride film 17a and silicon oxide film 1
In the photolithography process for forming the P ⁺ diffusion layer 6a, it is necessary to expect misalignment with the P ⁺ diffusion layer 7c. However, the CVD silicon oxide film 18a, CV
D silicon nitride film 17a and silicon oxide film 16a
Boundary of the region but which are formed, deviates to the inside of the P ⁺ diffusion layer 7c, the effect of suppressing the leakage weakens on these is not covered with the insulating film P ⁺ diffusion layer 7c. Conversely, if the boundary of the above-mentioned region shifts to the outside of the P ⁺ diffusion layer 7c, a portion without a channel stopper is formed under these insulating films, so that the leakage is likely to occur. For this reason, the photoresist 6b
Has a difficulty that almost no misalignment can be expected and that it must be formed only directly above the P ⁺ diffusion layer 7c. After the trench 9a and the P ⁺ diffusion layer 7d are formed, the silicon oxide films 12, 14a, 1
When removing 5a, this groove 9a is exposed to etching, and there is a problem that leakage due to damage increases.

[0007]

According to the method of manufacturing a semiconductor device of the present invention, a first insulating film, a first polycrystalline silicon film, a second insulating film, and a first insulating film are formed on a silicon substrate of one conductivity type. A step of sequentially forming a second polycrystalline silicon film, a step of forming a photoresist having a shape covering a region other than a region where an element isolation region is to be formed on the second polycrystalline silicon film, and using the photoresist as a mask Forming an opening by sequentially etching and removing the second polycrystalline silicon film, the second insulating film, and the first polycrystalline silicon film;
Forming a first one-conductivity-type diffusion layer in the opening and in a region where an element isolation region is formed on the surface of the silicon substrate by ion implantation through the first insulating film; and removing the photoresist. Forming a third insulating film on the entire surface; anisotropically etching the third insulating film and the first insulating film to form a spacer made of the third insulating film on the side wall of the opening; Removing the first insulating film on the bottom surface of the component, removing the second polycrystalline silicon film by anisotropic etching of silicon to form a self-aligned groove in the spacer on the silicon substrate, Forming a second one conductivity type diffusion layer at the bottom of the groove by ion implantation in a direction perpendicular to the surface, forming a fourth insulating film having a planarized surface over the entire surface, Until the upper surface of the polycrystalline silicon film is exposed. Fourth insulating film, and has spacers, and a step of the second insulating film is etched back, and removing the first polycrystalline silicon film.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIGS. 1 and 2, which are cross-sectional views in the order of steps for explaining a method of manufacturing a semiconductor device, an embodiment of the present invention firstly comprises first forming a first A silicon oxide film 2 having a thickness of about 20 nm is formed by thermal oxidation as an insulating film. Subsequently, a polycrystalline silicon film 3 having a thickness of about 200 nm is deposited as a first polycrystalline silicon film by a CVD method, and a second insulating film, a CVD silicon oxide film 4 having a thickness of about 100 nm, is formed. A polycrystalline silicon film 5 having a thickness of about 100 nm, which is a polycrystalline silicon film, is sequentially deposited. Next, a photoresist 6 covering the region other than the region where the element isolation region is formed is formed on the polycrystalline silicon film 5 (FIG. 1A).

Next, using the photoresist 6 as a mask, the polycrystalline silicon film 5, the silicon oxide film 4,
Then, the polycrystalline silicon film 3 is sequentially removed by etching to form an opening. The silicon oxide film 2 is exposed at the bottom of this opening. Next, using the photoresist 6 as a mask, for example, 30 keV, 1.0 × 10 ¹³
By ion implantation of boron of cm ⁻² , a P ⁺ diffusion layer 7a is formed on the surface of the silicon substrate 1 immediately below the opening.
The photoresist 6 is removed (FIG. 1B).

Next, a third insulating film having a thickness of 100 nm
A silicon oxide film 8 is deposited on the entire surface [FIG.
(C)].

Next, when anisotropic etching of the silicon oxide film is performed, the upper surface of the polycrystalline silicon film 5 is exposed, and a spacer made of a silicon oxide film 8a is formed on the side wall of the opening. The portion of the silicon oxide film 2 not covered by the spacer on the bottom surface of the silicon oxide film 2 is removed, and the P ⁺ diffusion layer 7a at a position self-aligned with the spacer is exposed [FIG.
(A)].

Next, when anisotropic etching of silicon is performed, a depth of about 0.5 μm penetrating the P ⁺ diffusion layer 7a is obtained.
Is formed in the silicon substrate 1 in a self-aligned manner with the spacer. At the same time, the polycrystalline silicon film 5 is removed. Next, at an incident angle perpendicular to the surface of the P-type silicon substrate 1, for example, 30 keV, 1.0 × 10 ¹³ cm ⁻²
Is performed to form a P ⁺ diffusion layer 7b at the bottom of the groove 9. Next, a film thickness of 1 μm as a fourth insulating film is formed.
2 m of silicon oxide film 10 is deposited on the entire surface [FIG.
(B)].

Next, the silicon oxide film is etched back until the upper surface of the polycrystalline silicon film 3 is exposed. The silicon oxide film 4 is completely removed by this etch back. Further, the inside of the groove 9 is filled with the silicon oxide film 10a, and the silicon oxide film 8a forming the spacer becomes the silicon oxide film 8b (FIG. 2C). After a while
By etching and removing the polycrystalline silicon film 2,
The formation of the element isolation region of the semiconductor device according to the present embodiment is completed (FIG. 2D).

[0015]

As described above, according to the method for manufacturing a semiconductor device of the present invention, the surface of the silicon substrate on the side wall portion of the groove is filled with the insulating film and formed on the one-conductivity-type silicon substrate. The first one conductivity type diffusion layer can be formed in a self-aligned manner, and a thick insulating film including this groove can be formed on the one conductivity type diffusion layer. For this reason, the minute leak along the groove, which has been a problem in the related art, is completely blocked by the first one-conductivity-type diffusion layer and the thick insulating film thereabove. Further, the first one-conductivity-type diffusion layer and the thick insulating film thereabove can be manufactured without considering misalignment because the self-alignment technique is frequently used, and the element isolation region can be easily miniaturized. Further, after forming the above groove,
The surface of the silicon substrate in the vicinity of the groove such as the first one-conductivity-type diffusion layer is not exposed to etching, and the influence of damage is completely eliminated.

[Brief description of the drawings]

FIG. 1 is a sectional view in the order of steps for explaining one embodiment of the present invention.

FIG. 2 is a sectional view in the order of steps for explaining the one embodiment.

FIG. 3 is a cross-sectional view in the order of steps for explaining a conventional method for manufacturing an element isolation region.

FIG. 4 is a cross-sectional view in the order of steps for explaining a conventional method for manufacturing an element isolation region.

[Explanation of symbols]

1 P-type silicon substrate 2, 12, 16, 16a Silicon oxide film 3, 5 Polycrystalline silicon film 4, 8, 8a, 8b, 10, 10a, 14, 14a, 1
5, 15a, 18, 18a CVD silicon film 6, 6a, 6b Photoresist 7a, 7b, 7c, 7d P ⁺ diffusion layer 9, 9a Groove 17, 17a CVD silicon nitride film

Claims (1)

(57) [Claims] A step of sequentially forming a first insulating film, a first polycrystalline silicon film, a second insulating film, and a second polycrystalline silicon film on a silicon substrate of one conductivity type; Forming a photoresist having a shape covering a region other than the region where the isolation region is formed on the second polycrystalline silicon film; using the photoresist as a mask, forming the second polycrystalline silicon film; A step of forming an opening by sequentially etching and removing the second insulating film and the first polycrystalline silicon film; and ion implantation through the opening and the first insulating film to form the silicon substrate. Forming a first one-conductivity-type diffusion layer in a region where the device isolation region is formed on a surface; removing the photoresist to form a third insulating film on the entire surface; 3 insulating film, and Anisotropically etching the first insulating film to form a spacer made of the third insulating film on a side wall of the opening, and removing the first insulating film on the bottom surface of the opening; Removing the second polycrystalline silicon film by anisotropic etching of silicon to form a self-aligned groove in the spacer in the silicon substrate; and ionization in a direction perpendicular to the surface of the silicon substrate. Forming a second one-conductivity-type diffusion layer at the bottom of the trench by implantation; forming a fourth insulating film having a planarized surface over the entire surface; A step of etching back the fourth insulating film, the spacer, and the second insulating film until an upper surface is exposed; and a step of removing the first polycrystalline silicon film. Semiconductor device manufacturing .