JP3196830B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device
In particular, trench isolation (STI;
The present invention relates to a semiconductor device suitable for preventing leakage current and enhancing the degree of integration in an isolation, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In general, an element isolation method ( local oxide) by selective oxidation widely used in semiconductor devices.
LOCOS) is caused by problems such as bird's beak due to a side oxide film, crystal defects in a silicon substrate due to stress of a buffer layer induced by heat treatment, and redistribution of ions implanted to prevent channel formation. This is a factor that hinders improvement of electrical characteristics and high integration of the semiconductor device.

[0003] As one method for improving the problem of the LOCOS method, a trench isolation (STI; shallow trench) in which a semiconductor substrate is etched to form a trench and an insulating film is buried in the trench to form an element isolation layer.
isolation ) has been proposed. This STI
Is not based on the thermal oxidation process as in the LOCOS in the formation of the element isolation.
The disadvantages of the OS method can be reduced to some extent. STI
According to the method, by adjusting the depth of the STI, 1G
Element isolation region (trench) having a width of 0.2 μm or less necessary for high integration of DRAM of a bit class or higher.
Can be formed.

FIGS. 7 and 8 are a plan view and a cross-sectional view for explaining a problem of a MOSFET manufactured by a conventional trench isolation method.

In FIG. 7, reference numeral 201 denotes an element region;
But the gate electrode, 203 is a contact hole, as shown in the figure, when the contact hole 203 is formed deviated to the outside of the device region 201, the element isolation region or separation
Since the trench 205 is etched, a leak current is generated when an element such as a MOSFET is formed.

[0006] As shown in FIG.
03 when the open, a portion where the isolation trench 205 rode, an interlayer insulating film 207 in the isolation trenches 205 et
It is etching, the over-etched region 208 of the diffusion layer 206. This is because the opening is deeper than the diffusion layer region of the diffusion layer 206, so that even if the contact burying member is buried therein, the burying member is directly buried in a portion deeper than the diffusion layer 206, so that electrical leakage occurs. Cause Reference numeral 204 denotes a silicon substrate.

In order to prevent such a mistake that said the contact hole 203 rests on isolation trenches 205, a method of fabricating smaller than the minimum size that is determined the isolation trenches 205 by photolithography is disclosed .

FIGS. 9 to 13 show the 1994 Symposium on VSI Technology ( Symp).
osium on VLSI Technology)
p. 19-20 "A Straight-Line -
Isolation and Trench-Gate
Transistor (SLIT) Cell for
The method shown in "Giga-bit DRAMs" will be described.

As shown in FIG. 9, first, a P-type silicon substrate 3 is formed.
01 was thermally oxidized to form a silicon oxide film 302, the element
The photoresist 303 for forming an isolation region is patterned. At this time, the photoresist 303, follower
It is the minimum size that can be formed by photolithography .
From this state, the silicon oxide film 302 is etched until the P-type silicon substrate 301 is exposed.

[0010] Subsequently, as shown in FIG.
04 was formed, and further, as shown in FIG. 11, dry etching
Etched back using grayed technique, a silicon oxide film 302
Is formed only on the side wall portion of the opening as the side wall silicon oxide film 304a.

Further, as shown in FIG. 12, a P-type silicon substrate 301 is etched to form a groove 305. here,
As shown in the figure, the groove 305 can be formed with an opening width smaller than the minimum dimension determined by lithography by an interval of the width S of the side wall silicon oxide film 304a .

[0012] From this state, a silicon oxide film (not shown), by performing etch back, the element buried silicon oxide film in the P-type silicon substrate 301
An isolation trench 306 is formed.

As described above, the element isolation trench 306 has a size smaller than the minimum dimension determined by lithography.
Can be formed , it is possible to secure a larger margin than the margin for the contact displacement shown in FIGS.

However, as shown in FIG.
In order to form an element such as T, it is necessary to form a sacrificial oxide film 307 for channel ion implantation (arrow B in the figure).

At this time, after the ion implantation, the sacrificial oxide film 3 is formed.
At the time of removing 07, the oxide film on the upper portion of the isolation trench 306 is simultaneously etched, and the concave portion 3 shown in FIG.
09 is formed.

When a MOSFET is formed in this state, a gate oxide film 310 and a gate electrode 311 are buried in the recess 309 as shown in FIG. Therefore, the gate electrode 31
When a voltage is applied to 1, the electric field at the corner of the concave portion becomes stronger than the original channel (electric field concentration region 312), and at this corner, the inversion layer is formed first. As a result, the threshold voltage of this portion decreases, and this MOS
Due to the electrical characteristics of the FET, the sub-threshold voltage changes, causing a current hump phenomenon in the sub-threshold region. Therefore, the leakage current increases and the on / off characteristics deteriorate. It should be noted that in FIGS.
Reference numeral 308 denotes an impurity implantation region.

As a method for avoiding the above problem,
There are the methods disclosed in JP-A-5-343515. This is shown in FIGS.

First, in FIG. 17, on a semiconductor substrate 401,
A first oxide film 402 made of a CVD oxide film is formed.
Next, an opening is formed by selectively removing the first oxide film 402 in a portion corresponding to a region including the element isolation region. This opening is set to the minimum resolution width in photolithography.

Next, a second oxide film 403 is formed on the entire surface including the opening. Etching back is performed from this state, and a side wall 404 is formed on the side wall of the first oxide film 402 as shown in FIG. Here, the first oxide film 4
02 and side wall 404 as a mask
Etching is performed on 401 to form a groove 408. Next, the first oxide film 4 on which the sidewalls 404 are formed
By implanting boron (B) using 02 as a mask,
A channel stopper region 409 is formed.

Next, as shown in FIG. 19, after removing the first oxide film 402 and the side wall 404, the semiconductor substrate 401 is thermally oxidized, and a third film made of a TEOS (tetraethoxysilane) film is formed. An oxide film 406 is deposited to form a thermal oxide film 405 . This is reflowed by heat treatment to planarize the surface of the third oxide film 406.

Next, the third oxide film 4 is formed by dry etching using a photoresist film 407 as shown in FIG.
06 is formed on the cap oxide film 410.

Next, as shown in FIG. 21, after removing the photoresist film 407, the cap oxide film 410 is isotropically etched to reduce the width of the photoresist film 407.

In this device isolation, the corner of the device isolation trench 306 (the electric field concentration region 31)
2, see FIG. 16 ), the deterioration of the sub-threshold characteristic at this portion does not occur. But,
Although the portion of the groove 408 is smaller than the minimum dimension obtained by lithography, the area occupied by the element isolation region is larger than this.

Further, since an isolation oxide film (thermal oxide film 405, cap oxide film 410) is formed on the semiconductor substrate 401 , irregularities are formed on the substrate, and a fine gate electrode on this upper layer is formed. However, there remains a disadvantage that it becomes difficult.

[0025]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been made in consideration of the above-described problems.
In I), even if the contact deviates from the element region and is formed on the element isolation region , it does not cause a leak current and avoids a shape problem that causes a hump in a sub-threshold current in the MOSFET. It is still another object of the present invention to provide a structure and a manufacturing method of a semiconductor element having improved characteristics without forming a step (concavo-convex) which makes it difficult to form a shape thereafter in an element isolation portion.

[0026]

According to a first aspect of the present invention, an element isolation insulating film is buried in an element isolation groove formed in an element isolation region of a semiconductor substrate. In the semiconductor device having the above structure, the element isolation groove has a first groove that forms the upper part of the groove and a second groove that forms the lower part of the groove.
Wherein the first groove has a wider groove width than the second groove, and is formed on the entire surface including the inside of the first groove.
Etch back the second silicon nitride film by a predetermined amount.
Leaving only the side wall portion of the first groove,
A film is formed , and the second silicon nitride film is formed in the first groove.
The portion where the recon film is not formed and the second groove are
The etching rate is faster than the second silicon nitride film
A semiconductor device is buried with a second silicon oxide film . The gist of the invention described in claim 2 of the present invention resides in that the second groove is formed in the first groove.
2. The semiconductor device according to claim 1, wherein the width of the portion where the silicon nitride film is not formed is smaller than the minimum resolution width in photolithography. The gist of the invention described in claim 3 of the present invention is as follows.
The depth of the first groove is such that the contact hole of the electrode to be formed on the element region is out of the element region and the second silicon oxide is formed.
3. The semiconductor device according to claim 1, wherein the depth of the capacitor film is larger than an expected depth of over-etching. According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which an element isolation of a semiconductor substrate is performed by an insulating film formed in an element isolation groove formed in an element isolation region of the semiconductor substrate. In the method, on a semiconductor substrate
The first silicon oxide film and formed by laminating a first silicon nitride film, they and the first silicon oxide film a first nitride Shi
Selectively removing a portion of the recon film corresponding to the element isolation region and forming a first groove in the semiconductor substrate; and forming a second silicon nitride film on the whole including the inside of the first groove.
And a second silicon nitride film is etched by a predetermined amount.
Back, leaving only the side wall portion of the first groove,
From this state, a first silicon nitride film is formed.
P-type silicon with the silicon nitride film and the sidewall silicon nitride film as masks.
Forming a second groove by etching the substrate;
And the first silicon nitride film and the first silicon oxide
And a step of removing the semiconductor film . The gist of the invention described in claim 5 of the present invention resides in that the second groove is formed in the first groove.
The method according to claim 4, wherein the width of the portion where the silicon nitride film is not formed is smaller than the minimum resolution width in photolithography. The gist of the invention described in claim 6 of the present invention is that the depth of the first groove is set in the second groove so that the contact hole of the electrode to be formed on the element region is out of the element region. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the buried insulating film is formed in advance to a depth larger than an expected depth to be over-etched.

According to the present invention, trench isolation (STI)
In the above method, even if the contact deviates from the element region and is formed on the element isolation region , no leak current is generated, and the sub-threshold current of the MOSFET formed by using the element isolation trench of the present invention is reduced. A semiconductor which avoids the problem of the shape that causes the occurrence of the step and does not form a step (unevenness) at the element isolation portion, which makes the subsequent formation of the shape difficult, thereby improving the electrical characteristics. An element structure and a manufacturing method can be provided.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are cross-sectional views showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps in order to explain the semiconductor device.

In the step shown in FIG. 1, the P-type silicon substrate 1
A first silicon oxide film 102 of about 10 μm is formed on the substrate 01 by thermal oxidation. Next, a first silicon nitride film 103 is formed to a thickness of about 100 μm by a CVD method. Subsequently, the photo more photolithography resist 1
An opening for forming the first groove 105 in a later step is formed in 04. Here, the opening width was set to the minimum resolution width in the photolithography process. Here, 0.2μ
m.

Next, in the step shown in FIG. 2, etching is performed using the photoresist 104 as a mask to transfer an opening to the first silicon oxide film 102, the first silicon nitride film 103, and the P-type silicon substrate 101. , The first groove 105 is formed.

The depth of the first groove 105 is selected from about 100 nm to about 150 nm . This depth is not only about 100 to 150 nm, but also the depth of the adjacent diffusion layer.
The depth and width of the element isolation region (silicon oxide film) 110 (described later) can be appropriately selected. This can be set in consideration of the depth of the above-described over-etched region.
This is because the features of the present invention can be utilized.

Subsequently, a second silicon nitride film 106 is formed on the entire surface including the inside of the first trench 105 by using the CVD method. The width of the first groove 105 and the second silicon nitride film 1
06, the element isolation region (oxidation
The width of the ( silicon film) 110 is determined. When the second silicon nitride film 106 is selected to have a thickness of about 50 nm , as described above, the first groove 1 determined by the photoresist 104 is used.
05 is about 0.2 μm, the width of the element isolation region (silicon oxide film) 110 formed in a later step is
It can be reduced to about 0.1 μm.

Next, as shown in FIG. 3, the second silicon nitride film 106 is etched back, leaving only the side wall portion of the first trench 105 to form a side wall silicon nitride film 106a. From this state, using the first silicon nitride film 103 and the side wall silicon nitride film 106a as a mask, the P-type silicon substrate 1
01 is etched to form a second groove 107.

Next, as shown in the step of FIG. 4, a second silicon oxide film 108 is formed so as to completely fill the second groove 107 by, for example, an apparatus using high-density plasma (HDP). I do. The film thickness is 400 to 500
About μm is appropriate.

Next, as shown in FIG. 5, the second silicon oxide film 108 is removed by polishing using a chemical mechanical polishing (CMP) method.
Silicon oxide film 108 is left in the second groove 107,
The buried silicon oxide film 109 is used.

In this CMP, the first silicon nitride film 103 functions as a CMP stop layer. this is,
Since the processing speed of the CMP are different 10 times a silicon oxide film and a silicon nitride film, the second silicon oxide film 108
After the polishing is completed, the first silicon nitride film 10
By exposing 3 , the processing hardly proceeds, so that it functions as a stop layer of CMP (processing).

In addition to the method of embedding the silicon oxide film using CMP, the second etching is performed using dry etching technology.
It is also possible to bury the silicon oxide film 108 in the second groove 107. At this time, the first silicon nitride film 1
03 functions as a stop layer. This is because the completion of the embedding of the second silicon oxide film 108 can be confirmed by detecting the exposure of the first silicon nitride film 103 .

Next, in the step shown in FIG. 6, the first silicon nitride film 103 is removed by wet etching, and the first silicon oxide film 102 is also removed by wet etching, so that the element isolation region (acid
(Silicon oxide film) 110 is formed. Element isolation region (acid
The protruding amount of the silicon oxide film 110 from the P-type silicon substrate 101 is 50 μm or less, and good flatness is obtained, which gives a sufficient margin for photolithography in a later step.

The flatness of the first silicon oxide film 10
2 and the thickness of the first silicon nitride film 103 and the wet etching amount of the first silicon oxide film 102 , and are not limited to only 50 μm.

After that, although not shown, a gate electrode and the like necessary for the device are formed, an interlayer insulating film mainly composed of a silicon oxide film is formed, and then a silicon nitride film and a silicon oxide film are selectively used for etching. With a specific etching method
A contact hole is opened in the interlayer insulating film .

As described above, the first silicon oxide film 102
Is etched under conditions that are selectively etched with respect to the first silicon nitride film 103 , so that even if a contact is formed off the element region, the side wall silicon nitride film 106a serves as an etching stop layer, It is possible to prevent formation of an over-etched portion of the contact that causes a leakage current.

[0042]

As described above, according to the present invention, the silicon nitride film is formed on the upper side wall of the groove formed in the element isolation region of the semiconductor substrate, and the silicon nitride film is formed inside and inside the silicon nitride film. Since a silicon oxide film is formed below the portion, the portion of the silicon nitride film is
This is a margin for misalignment of contact formation. The margin is 50 nm as in the embodiment.
This is a value sufficient for the alignment accuracy of the current exposure apparatus.

In the present invention, the upper part of the groove is a wide groove, and only the lower part is a narrow groove (less than the minimum resolution width of photolithography). As a result, the stress can be reduced and the leakage current caused by the stress can be suppressed, as compared with the case where the buried insulating film is buried uniformly in the narrow groove.

The silicon nitride film is formed only on the side wall above the trench. This is because the stress of the silicon nitride film is larger than that of the silicon oxide film. This is due to the provision of the film.

Therefore, for example, as compared with a structure in which the silicon nitride film is embedded in the entire groove or a case in which the silicon nitride film is embedded in the entire side wall not only above the groove but also below the groove.
Stress can be formed small. Therefore, it has the effect of suppressing the leakage current of the element isolation portion caused by the stress.

Further, since a silicon nitride film is formed in an element isolation portion in contact with an element region, it is necessary to perform channel implantation.
Even with the step of removing the sacrificial oxide and the oxide film formed by it becomes essential, not the portion of the silicon nitride film is reduced membrane, therefore, the corner portion is formed at an end of the element region, a gate electrode It is also possible to prevent the problem that the electric field is concentrated from the outside.

As a result, the characteristics of the MOSFET have the effect of suppressing the fluctuation of the sub-threshold characteristic, that is, the effect of suppressing the narrow channel effect and the hump phenomenon.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing step according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing step according to the embodiment of the present invention.

FIG. 7 is a plan view showing a conventional trench element isolation.

FIG. 8A shows a conventional trench element isolation .
FIG. 3 is a sectional view taken along line A ′ .

FIG. 9 is a cross-sectional view showing a manufacturing process of a conventional trench element isolation.

FIG. 10 is a cross-sectional view showing a manufacturing process of a conventional trench element isolation.

FIG. 11 is a cross-sectional view showing a manufacturing process of a conventional trench element isolation.

FIG. 12 is a cross-sectional view showing a manufacturing process of a conventional trench element isolation.

FIG. 13 is a cross-sectional view showing a manufacturing process of a conventional trench element isolation.

FIG. 14 is a cross-sectional view showing a problem of a conventional trench element isolation.

FIG. 15 is a cross-sectional view showing a problem of a conventional trench element isolation.

FIG. 16 is a cross-sectional view showing a problem of a conventional trench element isolation.

FIG. 17 is a cross-sectional view showing another problem of the conventional trench element isolation.

FIG. 18 is a cross-sectional view showing another problem of the conventional trench element isolation.

FIG. 19 is a cross-sectional view showing another problem of the conventional trench element isolation.

FIG. 20 is a cross-sectional view showing another problem of the conventional trench element isolation.

FIG. 21 is a cross-sectional view showing another problem of the conventional trench element isolation.

[Explanation of symbols]

Reference Signs List 101 P-type silicon substrate 102 First silicon oxide film 103 First silicon nitride film 104 Photoresist 105 First groove 106 Second silicon nitride film 107 Second groove 108 Second silicon oxide film 109 Embedded silicon oxide Film 110 element isolation region (silicon oxide film) 201 element region 202 gate electrode 203 contact hole 204 silicon substrate 205 isolation trench 206 diffusion layer 207 interlayer insulating film 301 p-type silicon substrate 302 silicon oxide film 303 photoresist 304 silicon oxide film 304a sidewall silicon oxide film 305 trench 306 isolation trenches 307 sacrificial oxide film 308 doped region 309 recess 310 gate oxide film 311 gate electrode 312 field concentration region 401 semiconductor substrate 402 first oxide film 403 Oxide film 404 sidewall 405 thermal oxide film 406 of the 2 third oxide film 407 a photoresist film 408 groove 409 channel stopper region 410 cap oxide film

Claims (6)

(57) [Claims] In a semiconductor device in which an element isolation insulating film is buried in an element isolation groove formed in an element isolation region of a semiconductor substrate, the element isolation groove has an upper part formed by the groove. A first groove, and a second groove that forms a lower portion of the groove, wherein the first groove has a wider groove width than the second groove, and includes an entire surface including the inside of the first groove. The second silicon nitride formed in
Etch back the film by a predetermined amount to the side of the first groove.
A sidewall silicon nitride film is formed leaving only the wall portion, and a portion of the first groove where the second silicon nitride film is not formed and the second groove are formed by the second nitride.
The second silicon oxide has a higher etching rate than the silicon film.
A semiconductor device characterized by being embedded in a con film . 2. The method according to claim 2, wherein the second groove is formed in the first groove.
2. The semiconductor device according to claim 1, wherein a width of a portion where the recon film is not formed is smaller than a minimum resolution width in photolithography. 3. The method according to claim 1, wherein the depth of the first groove is such that a contact hole of an electrode to be formed on the element region is out of the element region.
3. The semiconductor device according to claim 1 , wherein the second silicon oxide film is deeper than an expected depth of overetching. By wherein physical filled-in insulation film in the groove for element isolation formed in the isolation region of the semiconductor substrate, in the manufacturing method of a semiconductor device which performs isolation of the semiconductor substrate, a first oxide on a semiconductor substrate Silicon film and first silicon nitride
A first silicon oxide film and a first silicon nitride film corresponding to the element isolation region are selectively removed, and the first silicon oxide film and the first silicon nitride film are selectively removed from the semiconductor substrate. Forming a groove; and forming a second silicon nitride film over the entire surface including the inside of the first groove.
And etch back the second silicon nitride film by a predetermined amount.
Then, only the side wall portion of the first groove is left, and the side wall nitride silicon is formed.
From this state, a first silicon nitride film is formed.
P-type silicon substrate using the sidewall silicon nitride film as a mask
A step of etching a plate to form a second groove, and a step of removing the first silicon nitride film and the first silicon oxide film . Production method. 5. The method according to claim 5, wherein the second groove is formed in the first groove.
5. The method of manufacturing a semiconductor device according to claim 4, wherein the width of the portion where the recon film is not formed is smaller than the minimum resolution width in photolithography. 6. The insulating film buried in the second groove is over-etched so that a contact hole of an electrode to be formed on an element region deviates from the element region to a depth of the first groove. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed deeper than an expected depth.