JPS60226136A - Complementary type metal insulated semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To improve integration density at the inside or outside of well through effective prevention of latchup and compression of space around well by employing the trench structure for both well isolation region and inter-element isolation region. CONSTITUTION:A silicon dioxide film 12 is formed on the surface of an N type silicon wafer 1 and a silicon nitride film 13 is formed thereon. A second mask layer 13 is patterned, after a photo resist pattern 14 as the mask for ion implantation is removed, another photo resist pattern 17 is formed to the surface of wafer 1. After removing the photo resist pattern 17 used for formation of a hole 12a, a vertically elongated deep groove 9 is formed at the surface of wafer 1. A shallow groove 10 is formed to the region 80 where the inter-element isolation region is to be formed, by etching the exposed surface of wafer 1. A burying material 11 consisting of SiO2 is deposited to the entire part of surface, excessively deposited burying material 11 is etched back by the dry etching method. Thereby, the isolation regions 7, 8 can be completed.

Description

[Detailed Description of the Invention] Technical Field] The present invention is directed to a CM OS (Complementary
y MetalOxide Sem1conducto
r) The present invention relates to complementary metal-insulator semiconductor devices such as LSI, and particularly relates to techniques advantageous in terms of high integration and prevention of latch-up.

[Background technology]

In a complementary metal-insulator semiconductor device, a well of an opposite conductivity type is formed on one surface of a semiconductor substrate of a first conductivity type, and a metal-insulator semiconductor element of a first conductivity type and a metal-insulator semiconductor element of a second conductivity type are formed inside and outside the well. A plurality of metal-insulator semiconductor elements are each formed. Therefore, it is necessary to electrically isolate the inside and outside of the well and between each element.
(Loc-al Oxidation of 5ili
con) method was used.

However, isolation regions using the LOCO8 method have problems such as the occurrence of bird's beaks, and in particular, for well isolation regions for well isolation, in order to prevent latch-up, the periphery of the well must be provided with an optical width (for example, 7 ~8
However, it has been necessary to form a semiconductor device with a thickness of about .mu.m (#), which poses a problem in achieving high integration.

Therefore, a technique has been proposed in which the well isolation region is formed by a deep groove called a trench and an insulator filling the inside thereof. This is a method in which a groove with a width of about 1 μm and a depth of about 5 μm is formed, and then the groove is filled with silicon dioxide or the like. This method uses a vertically long separation region with a sufficient distance in the depth direction of the semiconductor substrate (see above, Nikkei Electronics, June 21, 1982 issue,
(See pages 146-151).

OBJECT OF THE INVENTION This invention is a step further than the proposed method (trench method), and its purpose is to provide a new technology in which both well isolation and element isolation are performed using the trench method. It is in.

Another object of the present invention is to provide a manufacturing technique that can form well isolation regions and element isolation regions in self-alignment lines using a relatively simple process.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, both the well isolation region and the element isolation region are constructed using the trench method, but while the well isolation region is as deep as or deeper than the well, the element isolation region The region is shallower than the depth of the well.

As a way to obtain such a configuration, 11 wells
1! Using a method of defining the valley grooves of the Tsukuda region and the element isolation region, that is, the deep grooves and the shallow grooves, on the same photomask,
Both areas are formed by Selfa Line.

〔Example]〕

FIG. 1 shows a cross-sectional structure of a CMO8LSI which is an embodiment of the present invention.

In FIG. 1, on one surface of an N-type silicon wafer 1, which is a semiconductor substrate of the J conductivity type, there is a P-type well 2, which is the opposite conductivity type, and inside the well 2 there is an N-channel MO.
8FET3, P channel MO8FE outside well 2
A plurality of T4s are each formed. Each of these MO8
The FET 3.4 consists of N" type or P" type source/drain regions 30, 40, a gate oxide film 5, and a gate 6 made of polysilicon or the like located thereon. Note that, although not shown, an insulating protective film such as phosphosilicate glass and aluminum wiring are further formed on the surface of the wafer 1.

Here, a vertically long well isolation region 7 deeper than the depth of the well 2 is provided around the well 2, and each MO8
An inter-element isolation region 8 shallower than the well 2 is formed between adjacent elements of the FETs 3.4. Both isolation regions 7 and 8 have mutually different depths, but their structures are common;
10, and a filling material 11 made of silicon dioxide, polysilicon, etc., which fills the grooves 9 and 10. [Filling material] As J, it is desirable to use a material with high insulating properties for j5, such as silicon dioxide, but polysilicon, etc., which can easily fill the trench, is also useful. It is necessary to form an oxide film on the inner surface of the trench and to oxidize the surface of the buried material. Such embedded material 11 is the groove 9
, 10, or a thin oxide film formed by thermal oxidation on the surface of the trenches 9 and 100 in order to improve the interface characteristics with the N'', P+ region, semiconductor substrate 1, and well 2 in contact with the trench. It is preferable to form (Sin, ).

Next, a manufacturing method suitable for obtaining the above-mentioned 0MO8LSI will be explained. FIGS. 2 to 8 are cross-sectional views showing the process flow.

(Refer to Figure 2) First, a silicon dioxide (s+0.) film 12, which will become a first mask layer, is formed on the surface of an N-type silicon wafer 1 by thermal oxidation or CVD. 2nd on J2
A silicon nitride (Si, N4) film 13 is formed as a mask layer. The silicon nitride film 13 is a selective mask layer that covers areas other than the portion 70 where the well isolation region is to be formed and the portion 80 where the element isolation region is to be formed. It is noted that the second mask layer 13 of silicon nitride can be readily patterned by conventional photoetching techniques, in which case portions 70 and 80 are defined on the same photomask. This is part 70 and part 80
This has the advantage of reducing the mask alignment margin between the two to zero.

(See FIG. 3) After patterning the second mask layer 13, the photoresist pattern (not shown) used therein is removed, and a new photoresist pattern 14 is created for forming the P-type well 2.
form. It goes without saying that photo 1/cyst pattern 4 covers the area other than the area where well 2 is to be formed. Using this photoresist pattern 14 as a mask, ions are implanted into the surface of the silicon wafer to produce P such as boron.
A mold impurity 15 is introduced. A region 16 indicated by a broken line indicates a portion into which a P-type impurity is introduced. In addition, as described later in Example 2, the impurity 15 is introduced by Si, N,
It may be performed before forming the film 13.

(See FIG. 4) After removing the photoresist pattern 14 as a mask for ion implantation, another photoresist pattern 17 is formed on the surface of the silicon wafer 1. The photoresist pattern 17 is used to form holes 12a in the lower first mask layer 2 corresponding to the holes 13a in the upper second mask layer 13 in order to form the well isolation region 7. Therefore, photoresist pattern 1
The open end 17a of No. 7 is located on the second mask 1@13 adjacent to the hole 13a. Photoresist pattern 17
need only expose the portion 70 where the well isolation region is to be formed and cover the portion 80 where the element isolation region is to be formed;
Mask alignment for forming the photoresist pattern 17 does not require much precision. Note that the first mask layer 12
The holes 12a can be formed by either wet or dry etching.

(Refer to FIG. 5) After removing the photoresist pattern 17 used for forming the hole 12a, a vertical pattern is formed on the surface of the silicon wafer 1 using the first and second mask layers 12.13 as masks for etching. A deep groove 9 is formed. To form this groove 9, anisotropic etching with almost no side etching, such as reactive ion etching, is used. By etching for forming the groove 9, the second mask layer]3 and the first mask Iv of the portion 80 where the element isolation region is to be formed are etched.
12 is also slightly etched, but it can be left even after etching by setting the etching selection ratio.

After forming the groove 9, the P-type impurity introduced into the surface is stretched and diffused to a depth of, for example, 3 μm.
A P-type well 2 of about m is formed.

In this case, since the deep grooves 9 are formed prior to the well expansion and diffusion process, the side periphery of the P-type well 2 can be reliably defined by the grooves 9. If the outward diffusion of the P-type impurity during the stretching diffusion is a problem, a thin SiO2 film may be formed on the inner surface of the groove 9 before the stretching diffusion.

(Refer to FIG. 6) Next, the silicon dioxide remaining in the portion 80 where the element isolation region is to be formed is removed using the upper second mask WI113.
After etching is performed using a mask as a mask, the exposed surface of the silicon wafer 1 is etched to form a shallow groove 10 having a depth of, for example, about 1 μm in a portion 80 where an element isolation region is to be formed. When etching this shallow (@10), the already formed deep groove 9 itself is also etched further, but an additional problem arises.
The silicon dioxide etching performed prior to the zero etching may be wet or dry etching.

(See FIG. 7) After forming the deep grooves 9 and the shallow grooves 10, the entire surface of the silicon wafer 1 is coated with S+0. A buried material consisting of [1] is deposited. To fill the trench, it is necessary to deposit CVD to a thickness that is at least 372 times the width of the trench.

Moreover, if each port 9, 10 is made to have approximately the same groove width, the grooves X9, 10 can be filled in by one filling process regardless of the depth. In order to more easily embed each port 9.10, it is preferable to deposit the embedding material 11 under conditions with good coverage, such as CVD at high temperature and low pressure. In this way, by the − times of embedding processing,
Since two types of grooves 9 and 10 having different depths can be filled, the process can be simplified accordingly.

(See FIG. 8) Next, the excess deposited material 11 is etch-packed by dry etching. In this case, the second mask layer 13 made of silicon nitride functions as an etching stopper.

As a result, each separation region 7, 8 is completed. Then Si
3N4 film 13 + 5 lot film] 2 is removed, and then the gate oxide film 5. is removed by normal CMOS process. A gate 6 made of polysilicon or the like, N+ type or P" type source/drain regions 30, 40, and an insulating protective film and aluminum wiring (not shown) are formed. Thereby, a CMO8LSI as shown in FIG. 1 is formed. complete.

[Example 2] FIGS. 9 to 11 are cross-sectional views showing a process flow when the well-forming impurity 15 in Example 1 is introduced before forming the Si3N4 film 13.

(Refer to Figure 9) First, a 5102 film 12, which will become a first mask island, is formed on the surface of an N-type silicon wafer 10 by thermal oxidation or CVD, and then a P-type well 2 is formed. A photoresist pattern 14 is formed for this purpose.

(See FIG. 10) Using the photoresist pattern 14 as a mask, the Sin film 12 is lightly etched by dry etching or wet etching to form a step 12b. This is to make it easier to detect a signal of loosening of mask alignment in the next photoresist process. Thereafter, using the photoresist pattern 14 as a mask, a P-type impurity J5 such as borine is introduced into the surface of the silicon wafer 1 by ion implantation.

A region 16 indicated by a broken line indicates a portion into which a P-type impurity is introduced.

(Referring to FIG. 11) A Si3N4 film 13, which is a second mask layer, is formed on the Si film 12, and a portion 70 where a well isolation region is to be formed and an isolation region between elements are formed by photoetching. 8i of the portion 80, the N4 film is removed by etching.

Thereafter, the 0MO8LSI as shown in FIG. 1 is completed by the same process as shown in FIGS. 4 to 8 of Example J].

[Example 3] In order to make the electrical isolation more complete, a high concentration of P was added under the element isolation insulating film of the N-channel MO8FET.
It may be necessary to form regions of the mold, so-called channel stopper regions.

FIG. 12 shows one method of introducing a channel stopper. After completing the process shown in FIG. 8 in [Embodiment 1], parts other than the part where the P-type well is to be formed are masked with photoresist 18 or the like. Next, P-type impurity 19 such as boron is ion-implanted with high energy. At this time, by setting the implantation energy so that the peak of the impurity distribution is directly under the element isolation insulating film 8, a channel stopper region 20a made of boron with a high concentration can be formed.

In areas other than the isolation region 8, the implanted boron ions are distributed in the busier area 20b, but this does not occur particularly in terms of device characteristics. Thereafter, the photoresist 18 is removed, and an 0MO8LSI is completed using the same process as in Example 1. Note that the photoresist 18 must be set to have a thickness sufficient to block the impurity ions 19.

〔effect〕

(1) Since both the well isolation region and the element isolation region have a trench structure, launch-up can be effectively prevented, the space around the well can be reduced, and the degree of integration of elements inside and outside the well can be improved. I can do it.

(2) Since the element isolation region is shallower than the well isolation region, the substrate of each element is common, and a substrate bias can be easily applied.

(Since the valley grooves of the 31-well isolation region and the element isolation region, that is, the deep grooves and the shallow grooves, are defined on the same photomask, both regions can be formed by self-line.

(4) Since the deep trench and the shallow trench are filled in the same process, the filling process is simplified and the entire process is that much simpler.

Although this invention has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above-mentioned Examples and can be modified as much as possible without departing from the gist thereof. . For example, a structure having an oxide film formed by the usual LOCO8 method as a wide area area (field Sin) where wiring runs in peripheral circuits etc. may also be used (4°). In addition to a silicon wafer, an epitaxial wafer having an epitaxial layer on the substrate can be used. Furthermore, the semiconductor substrate 1 can be of P type and the well 2 can be of N type. Also, only the P type well 2 can be formed. , in addition to the so-called single-well method, N-channel MO8FET and P-channel MO8FET
It is also possible to adopt a so-called double-well system in which each characteristic of the 8FETs can be optimized independently.

[Application field]

The present invention can be applied to complementary metal-insulator semiconductor devices such as 0MO8LSI, particularly highly integrated and high-performance devices, to obtain great effects.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIGS. 2 to 8, 8, and 12 are sectional views showing the process flow of the 0MO8LSI shown in FIG. be. J...Semiconductor substrate (silicon wafer), 2...Well, 3...N channel MO8FET, 4...P channel IVIO8FET, 30.40...Nose/drain region, 5...Gate oxidation Membrane, 6... Gate, 7
... well isolation region, 70... portion where well isolation region is to be formed, 8... element isolation region, 80... portion where element isolation region is to be formed, 9... deep groove, 10
...shallow groove, 11...embedding material, 12...first
mask layer (SiOJ, 12b... level difference for mask alignment signal detection, 13... second mask layer (Si3N
4), 14... Photoresist pattern, ]5...
P-type impurity, 16... Impurity introduction part, 17.18.
... Photoresist pattern, ]9... P-type impurity, 2
0a...Channel stopper area. Fig. 1 Fig. 2〉/ Fig. 31￥1 No. 41; 1 Fig. 5 Bird / Fig. 6 Fig. 7 Zone No. 8U9'l / / Fig. 9 / 4 / Fig. 10 Fig. 11 Fig. 12L I 1

Claims (1)

[Claims] 1. A well of a second conductivity type, which is an opposite conductivity type, is provided on one surface of a semiconductor substrate of a first conductivity type, and a metal-insulator semiconductor element of a conductivity type [ ] and a second conductivity type are provided inside and outside the well. Each has a plurality of metal-insulator semiconductor elements of a conductive type, and a well isolation region for vertically separating the wells, which is about the same depth as the well or deeper than the well, in the peripheral part of the well, and further between each of the plurality of elements. Each of the semiconductor substrates is provided with shallow inter-element isolation regions for isolating adjacent elements, and each of these isolation regions is constituted by a trench formed on one surface of the semiconductor substrate and a embedding material for filling the trench. A complementary metal-insulator semiconductor device characterized by: 2, W, On one side of the semiconductor substrate of the 1 conductivity type, there is a well of the second conductivity type of the opposite conductivity type, and inside and outside of this well there is a metal insulator semiconductor element of the first conductivity type and a metal insulator of the second conductivity type. Each of the plurality of semiconductor elements has a plurality of semiconductor elements, and a well isolation region for vertically separating the wells having a depth equal to or deeper than the depth of the well in the peripheral portion of the well, and further between adjacent elements between each of the plurality of elements. A complementary metal-insulator semiconductor device comprising at least the following steps in manufacturing a complementary metal-insulator semiconductor device each having a shallow inter-element isolation region for isolating the elements. Manufacturing method. (One surface of the Al semiconductor substrate of the first conductivity type is covered with a first mask layer, and a second mask layer is formed on the first mask layer to cover the area other than the portion where each isolation region is to be formed. (Bl) Using a part of the second mask layer as part of a mask for etching, a hole is formed in a part of the first mask layer where the well isolation region is to be formed, and then,
A step of forming a vertically deep groove in a portion where the well isolation region should be shaped by using the first mask layer having the hole and the second mask layer partially covering the hole as a mask for etching. (Q) A step of stretching and diffusing impurities for forming a well, which were selectively introduced before step (■) step 8, into one surface of the semiconductor substrate after step [F]) to form a well of the second conductivity type. ] A shallow groove is formed in a portion where the element isolation region is to be formed by etching the semiconductor substrate using the second mask layer as a mask. After the fEI OD+ step, a step of filling the shallow trench and deep trench with a filling material.