JPH07161806A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To achieve a high density of a semiconductor device by a method wherein an alignment margin between an element-isolation trench and a well- isolation trench is reduced to zero. CONSTITUTION:A shallow trench 26 is formed by using a reticle on which both and element-isolation-trench pattern and a well-isolation-trench pattern have been drawn. Then, an SiO2 film 23 whose step coverage is excellent is formed, and a well-isolation pattern is then transferred by using a reticle in which a portion corresponding to an alignment error has been expanded. The well-isolation pattern by which a deep trench is to be formed by this PR process is exposed completely. In addition, only Si in the bottom part of the well- isolation pattern is exposed by an SiO2 RIE operation. Then, when a deep trench 27 is etched, the shallow element-isolation trench and the deep well- isolation trench can be formed at an alignment margin of zero.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using trench isolation.

[0002]

2. Description of the Related Art With the increase in density of semiconductor devices, the LOCOS element isolation conventionally used is approaching its limit. The trench element isolation method that enables finer element isolation than the LOCOS system is effective as the next element isolation. Also, the current circuit is mainly composed of CMOS, and the separation between the N well region and the P well region is also LOCOS.
The system is used. Area reduction can be achieved by using trench isolation for well isolation. Therefore, in the next semiconductor device, it is essential to use trench isolation for both element isolation and well isolation.

However, the element isolation trench and the well isolation trench have different depths. 3 for element isolation
000-5000 angstroms, 2 for well separation
~ 4 μm is required.

A manufacturing method using the prior art is shown in FIG.
According to the conventional manufacturing method, as shown in FIG. 2A, first, as shown in FIG.
The iO ₂ film 21 is formed by thermal oxidation or the CVD method. Next, after applying the resist 22, a resist pattern is formed using a reticle having a trench pattern for element isolation. The opening 10 is a pattern for forming a shallow trench for element isolation.

Next, as shown in FIG. 2B, RIE
The SiO ₂ film is etched using (reactive ion etching). Then, the resist is stripped off and SiO _{2 is} removed.
A trench etching mask is formed. Using this SiO ₂ trench etching mask, the shallow trench 32 having a depth of 4000 Å is etched. After the cleaning, as shown in FIG. 2C, a CVD-SiO ₂ film 24 having a thickness of about 5000 Å is formed, and the resist 2 is formed.
The well separation pattern consisting of 5 is transferred.

Next, SiO ₂ RIE is performed to etch the SiO ₂ film 21 and the resist is stripped to form a SiO ₂ trench etching mask. The deep trench 31 is etched using this SiO ₂ mask. In this case, the shallow trench 32 is covered with the CVD-SiO ₂ 24 and is not etched. After etching the deep trench 31, the SiO ₂ mask is removed by wet etching. In this way, two types of trenches having different depths are formed.

[0007]

In the method according to the prior art, an alignment error occurs between the device isolation trench pattern and the well isolation trench pattern. As shown in FIG. 3, the source or drain area of the MOS transistor is reduced due to the alignment error. When the contact hole 34 for the source or the drain is formed when the alignment error occurs, the contact bottom portion is displaced on the well isolation trench 31 as shown by a portion A surrounded by a dotted line. As a result, the contact area becomes insufficient and the transistor characteristics change, resulting in a decrease in yield. Considering this point,
The source or drain in contact with the well isolation trench 31 is enlarged to eliminate the influence of alignment error.
However, by considering the margin, the integration density is reduced. Therefore, it is necessary to make the alignment margin of the element isolation trench 32 and the well isolation trench 31 zero, that is, self-aligned.

In FIG. 3, 33 is a gate and 35 is an interlayer insulating film.

[0009]

The present invention uses a reticle in which both shallow trenches for element isolation and deep trenches for well isolation are simultaneously drawn. First, a SiO ₂ etching mask pattern is formed using a reticle having both trench patterns. A shallow trench is formed using this SiO ₂ etching mask. In this process, a deep trench pattern and a shallow trench are also formed. Next, HTO film with excellent step coverage (CV of high temperature growth
D-SiO ₂ film) is grown to 500-1000 angstroms entire surface. Then, the pattern of the deep trench is transferred using a reticle in which only the deep trench pattern is drawn. On the reticle used in this case, a pattern wider than the actual trench width by an amount corresponding to the alignment error is drawn. In this resist process, only the deep trench pattern portion formed first is opened. Moreover, the opening is wide corresponding to the alignment error. Therefore, the deep trench pattern formed first is completely exposed even if there is a misalignment. Si in this state
When O ₂ RIE is performed, Si is exposed only at the bottom of the pattern in which the deep trench initially formed is to be formed. After this Si
The Si trench is formed under the condition that the selection ratio to O ₂ is high. By this series of processes, shallow trenches and deep trenches can be formed by self-alignment.

[0010]

EXAMPLES Next, examples of the present invention will be described.

FIG. 1 is a sectional view showing each step of one embodiment of the present invention. First, as shown in FIG. 1A, a SiO ₂ film 2 serving as a trench etching mask is formed on a Si substrate 20.
1 is formed by thermal oxidation or the CVD method. next,
After the resist 22 is applied, a resist pattern is formed using a reticle having both element isolation trench patterns and well isolation trench patterns. The opening 10 is a pattern for forming a shallow trench for element isolation, and the opening 11 is a pattern for forming a deep trench for well isolation.

Next, as shown in FIG. 1B, RIE
(Reactive ion etching) is used to form the SiO ₂ film 21.
To etch. Then, the resist is peeled off, and Si
An O ₂ trench etching mask is formed. This SiO
₂ Form shallow trenches using a trench etching mask. In this state, the pattern for forming a deep trench is also a shallow trench.

Next, as shown in FIG. 1C, a HTO film (high temperature growth SiO ₂ ) 23 having good step coverage characteristics is grown on the entire surface through a cleaning process. Then, the well separation pattern made of the resist 25 is transferred by the PR process. In this case, the pattern size is a reticle that is wider than the actually required trench width by an alignment error. Since the alignment accuracy in the current stepper is about 0.15 μm, a pattern expanded by 0.15 μm on one side and 0.3 μm in total is transferred. The well separation pattern formed first is completely exposed without being covered by the resist 25. Then, when SiO ₂ RIE is performed, it becomes as shown in FIG. Here, the Si substrate 20 is exposed only at the bottom of the pattern that is to be the well isolation trench formed first. After the resist is stripped off, a deep trench is formed.
As shown in (e), the shallow trench 26 and the deep trench 27 can be formed. In addition, both trenches can be brought close to the size where the minimum pattern can be formed without the need to consider the alignment margin.

Deep trench etching requires highly selective Si etching with respect to the SiO ₂ mask. This etching can be realized by an etching apparatus using a magnetron RIE or an ECR system plasma source under the etching conditions of an etching pressure of 5 to 20 wTorr and a chlorine / oxygen mixed gas (oxygen addition amount: 3 to 30%).

In the method of this embodiment, since the number of PRs or the number of steps is not increased, the manufacturing cost is the same as the conventional one. Moreover, well isolation trenches and element isolation trenches having different depths can be arranged with zero alignment margin. As a result, the density of the semiconductor device can be increased.

Further, in this embodiment, SiO ₂ is used for simplicity.
Although the etching mask has been described, it may be a multilayer film in which polysilicon, a silicon nitride film, or the like is disposed under the SiO ₂ .

[0017]

As described above, when the present invention is used,
It is possible to form trenches having different depths with zero margin for alignment error, that is, self-alignment. As a result, the density of the semiconductor device can be increased. Further, by using the present invention, the number of processes and the number of PRs do not increase, and the cost does not increase.

[Brief description of drawings]

FIG. 1 is a sectional view of each step showing one embodiment of the present invention.

FIG. 2 is a cross-sectional view of each step showing the manufacturing method when the conventional technique is used.

FIG. 3 is a cross-sectional view of a semiconductor device manufactured using a conventional technique.

[Explanation of symbols]

10 Shallow Trench Pattern 11 Deep Trench Pattern 20 Si Substrate 21 SiO ₂ Film 22, 25 Resist 23 HTO Film 24 CVD-SiO ₂ Film 26 Shallow Trench 27 Deep Trench 31 Well Isolation Trench 32 Element Isolation Trench 33 Gate 34 Contact Hole 35 Interlayer Insulation film

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device using trench isolation, wherein a reticle in which both a shallow element isolation trench pattern and a deep well isolation pattern are drawn is used to pattern both patterns at the same time. After that, a shallow element isolation trench is formed, a mask film excellent in step coverage is formed, and a step of transferring a well isolation pattern expanded by an alignment error from the deep well isolation pattern, and after the transfer step, Etching the mask film and subsequently forming a deep well isolation trench. 2. A method of manufacturing a semiconductor device using trench isolation, wherein a SiO ₂ etching mask pattern is formed on a Si substrate using a first reticle in which both shallow trenches for element isolation and deep trenches for well isolation are simultaneously drawn. And a step of forming a shallow trench using the SiO ₂ etching mask, and a high temperature growth CVD-SiO having excellent step coverage.
₂ step of growing the entire surface of the film, step of transferring the deep trench pattern using the second reticle in which only the deep trench pattern is drawn, and etching of the CVD-SiO ₂ film to form the deep trench formed first S only on the bottom of the pattern to be formed
A method of manufacturing a semiconductor device, comprising: exposing an i-substrate; and forming a deep trench by etching. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a pattern wider than the actual trench width by an alignment error is drawn on the second reticle.