JP3321613B2 - Method for forming shallow and deep grooves in silicon substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention forms two types of trenches (shallow trenches and deep trenches) having different depths which are applied to the manufacture of, for example, complementary MOS field effect transistors and bipolar transistors in the same silicon substrate. The present invention relates to a method for forming a shallow groove and a deep groove in a silicon substrate.

[0002]

2. Description of the Related Art In recent years, a method of electrically isolating components in an integrated circuit by a groove dug in a silicon substrate has been adopted in order to improve the performance and density of the silicon integrated circuit. Was. Moreover, it has become necessary to form two types of grooves having different depths (shallow groove and deep groove) in order to satisfy higher requirements.

FIG. 23 is a sectional view showing an example of a configuration of a complementary field effect transistor using a shallow groove and a deep groove in a silicon substrate. In FIG. 1, a high-concentration impurity diffusion layer 2 of the opposite conductivity type is formed on a silicon substrate 1, and an element formation region A 'on an n-well 3' formed on the impurity diffusion layer 2 has a p ⁺ source. A p-channel MOS field-effect transistor composed of the drain diffusion layer 15, the gate insulating film 17, and the gate electrode 18 is formed;
The element formation region A "on the p well 3" has an n ⁺ source
An n-channel MOS field-effect transistor including a drain diffusion layer 16, a gate insulating film 17, and a gate electrode 19 is formed.

A region B located between the element formation region A 'and the element formation region A "has a reverse conductivity type n.
A deep groove for separating the well 3 'and the p-well 3 "is formed, and a shallow groove for separating the elements in the respective n-well 3' and p-well 3" is formed in the region C. Is formed. In addition, in a bipolar transistor other than a complementary field-effect transistor, a shallow groove and a deep groove are formed on the same silicon substrate, for example, a deep groove is used for separating between elements and a shallow groove is used for separating between a base and a collector in the element. Has a wide application range for manufacturing silicon integrated circuits.

Next, a conventional method of forming a shallow groove / deep groove in a silicon substrate will be described with reference to FIGS. 24 to 28 and FIGS. 29 to 33. 24 to 28
FIG. 4 is a cross-sectional view of a step for explaining a first forming method in which a deep groove is formed first and a shallow groove is formed later. In these drawings, first, as shown in FIG. 24, a high-concentration impurity diffusion layer 2 of the opposite conductivity type is formed on a silicon substrate 1, and a silicon layer 3 is epitaxially grown on the impurity diffusion layer 2. Although the impurity diffusion layer 2 and the silicon layer 3 are not essential, they are often used in a high-performance silicon integrated circuit using both shallow grooves and deep grooves. Next, an insulating film 7 is formed on the silicon layer 3 by thermal oxidation, chemical vapor deposition (CVD), or the like, and a resist pattern 8 for forming a deep groove is formed on the insulating film 7 by using a known lithography technique. To form

Next, as shown in FIG. 25, the insulating film 7 is etched using the resist pattern 8 as a mask, the resist pattern 8 is removed, and then the region B is etched using the insulating film 7 as a mask.
Then, a deep groove is formed by etching to a depth penetrating the high concentration impurity diffusion layer 2. Here, if necessary, a channel cut impurity diffusion layer 9 is formed at the bottom of the deep groove by ion implantation. Next, as shown in FIG. 26, a resist pattern 6 for forming a shallow groove which covers the element formation region is formed on the insulating film 7 by using a lithography technique.

Next, as shown in FIG. 27, after the insulating film 7 is etched using the resist pattern 6 as a mask, the resist pattern 6 is removed. Thereafter, as shown in FIG. 28, a shallow groove is etched in the region C using the insulating film 7 as a mask,
A structure in which shallow and deep grooves are formed in the same substrate has been obtained.

FIG. 29 to FIG. 33 are cross-sectional views illustrating steps for explaining a second forming method of forming a shallow groove first and forming a deep groove later. In these drawings, first, as shown in FIG. 29, a high-concentration impurity diffusion layer 2 of the opposite conductivity type is formed on a silicon substrate 1, and a silicon layer 3 is epitaxially grown on the impurity diffusion layer 2. As described above, the impurity diffusion layer 2 and the silicon layer 3 are not essential. Next, an insulating film 4 is formed on the silicon layer 3 by thermal oxidation, CVD, or the like, and a resist pattern 6 for forming a shallow groove covering the element formation region is formed on the insulating film 4 by using a known lithography technique.
Then, the insulating film 4 is etched using the resist pattern 6 as a mask.

Next, as shown in FIG.
Is removed, a shallow groove is etched in the region C using the insulating film 4 as a mask. Next, as shown in FIG. 31, an insulating film 7 is formed on the entire surface by the CVD method, and a resist pattern 8 for forming a deep groove is formed by using a lithography technique. Next, FIG.
As shown in FIG. 2, the insulating film 7 is etched using the resist pattern 8 as a mask, and the resist pattern 8 is removed.
Next, using the insulating film 7 as a mask, a deep groove is formed by etching to a depth penetrating the high-concentration impurity diffusion layer 2, and a channel-cut impurity diffusion layer 9 is formed at the bottom of the deep groove by ion implantation as needed. .

[0010] Thereafter, the insulating film 7 is removed to obtain a structure in which shallow and deep grooves are formed in the same substrate as shown in FIG. When the insulating film 7 is used as a part of the field insulating film in a subsequent step, the insulating film 7 need not be removed.

[0011]

However, in the above-mentioned first conventional forming method, since the deep groove is already opened when the shallow groove resist pattern 6 is formed,
The resist forming the resist pattern 6 could not be applied to a uniform thickness due to the flow of the resist into the deep groove. As a result, there is a problem that the pattern dimensions of the element formation region cannot be formed accurately. Further, it has been practically impossible to form a pattern in which the end of the element formation region A exists in the deep groove region B.

Further, in the above-described second conventional forming method, when the deep groove resist pattern 8 is formed, there is a step formed by adding the shallow groove depth and the thickness of the insulating film 4 to the underlying layer. When the element formation region A is close to the device, the resist thickness in the deep groove region B becomes uneven. As a result, there is a problem that the pattern size of the deep groove cannot be formed accurately. Similarly, when the element formation region A and the deep groove region B are close to each other, the insulating film 7 is formed at a stepped portion.
It was necessary to perform the processing, and accurate processing could not be performed.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method for forming a resist pattern and a subsequent etching of an insulating film on a silicon substrate with little difficulty. An object of the present invention is to provide a groove / deep groove forming method.

[0014]

In order to achieve the above object, the present invention provides a method of temporarily transferring a shallow groove resist pattern to a thin silicon film or a multilayer film having a silicon film as an uppermost layer. After the formation of the deep groove resist pattern and the deep groove etching are performed first, the shallow groove etching is performed using the shallow groove pattern transferred to the silicon film or the like.

[0015]

In the present invention, in both the case of forming a shallow groove resist pattern and the case of forming a deep groove resist pattern, an accurate resist pattern can be formed because the step of the base is small. Further, even in the etching subsequent to the pattern formation, a problem hardly occurs because the steps are small. As a result, the shallow groove and the deep groove can be formed with accurate dimensions without being affected by the positional relationship between the shallow groove and the deep groove.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. (Embodiment 1) FIGS. 1 to 5 are cross-sectional views of steps for explaining a first embodiment of a method for forming a shallow groove and a deep groove in a silicon substrate according to the present invention. First, as shown in FIG. 1, a high-concentration impurity diffusion layer 2 of the opposite conductivity type is formed on a silicon substrate 1, and a silicon layer 3 is epitaxially grown on the impurity diffusion layer 2. Although the impurity diffusion layer 2 and the silicon layer 3 are not essential, they are often used in a high-performance silicon integrated circuit using both shallow grooves and deep grooves. Next, a silicon oxide film 4 is formed on the silicon layer 3 by thermal oxidation or chemical vapor deposition (CVD), and a polycrystalline silicon film 5 is formed on the silicon oxide film 4 by CVD or the like. .

Since the silicon oxide film 4 serves as a mask for later etching of the shallow groove, it may be thinner than the depth of the shallow groove. Further, since the polycrystalline silicon film 5 serves as a mask when the silicon oxide film 4 is etched later,
It may be thinner than the silicon oxide film 4. Subsequent to the formation of these films, a resist pattern 6 for forming a shallow groove covering the element formation region is formed by using a known lithography technique, and using this resist pattern 6 as a mask, SiCl ₄ , Cl is used.
_The polycrystalline silicon film 5 is etched by a reactive ion etching method using a chlorine-based gas such as ₂ (hereinafter referred to as a chlorine-based RIE method). Since the pattern formation and the etching are performed on a flat surface, no problem occurs due to the unevenness of the base.

Next, after removing the resist pattern 6, FIG.
As shown in FIG. 1, a silicon oxide film 7 serving as a mask for deep trench etching is formed on the entire surface of the silicon oxide film 4 on which the polycrystalline silicon film 5 is formed by CVD or the like, and lithography is performed on the silicon oxide film 7. A deep groove forming resist pattern 8 is formed by using a technique. Since the underlying step at the time of this pattern formation is only due to the thin polycrystalline silicon film 5, there is almost no problem caused by the unevenness of the underlying.

Next, a silicon oxide film 7 and a silicon oxide film are formed by a reactive ion etching method (hereinafter referred to as a fluorine-based RIE method) using a fluorocarbon-based gas such as CHF ₃ or C ₂ F ₆ using the deep groove resist pattern 8 as a mask. 4 are sequentially etched to expose the surface of the silicon layer 3 as shown in FIG. 3, and then the resist pattern 8 is removed. At this time, if the deep groove region and the element formation region overlap,
Between the etching of the silicon oxide film 7 and the etching of the silicon oxide film 4, the polycrystalline silicon film 5 needs to be etched by a chlorine-based RIE method. Subsequently, a deep groove is etched in the region B using the silicon oxide film 7 as a mask. This etching is performed by using a chlorine-based RIE method to a depth penetrating the high-concentration impurity diffusion layer 2. Then, if necessary, a channel-cut impurity diffusion layer 9 of the same conductivity type as the silicon substrate 1 is formed in the bottom of the deep groove by ion implantation.
To form

Next, the silicon oxide film 7 is etched and removed by a fluorine-based RIE method to expose the polycrystalline silicon film 5 as shown in FIG. 4, and the polycrystalline silicon film 5 is used as a mask to oxidize by a fluorine-based RIE method. The silicon film 4 is etched. Note that the etching of the silicon oxide film 7 and the silicon oxide film 4 can be performed continuously without interruption in the middle. Thereafter, as shown in FIG. 5, a shallow groove is etched in the region C of the silicon layer 3 by a chlorine-based RIE method using the silicon oxide film 4 as a mask to obtain a structure in which the shallow groove and the deep groove are formed in the same substrate. . Note that the polycrystalline silicon film 5 is removed during the shallow groove etching.

In the first embodiment, the single-layer silicon oxide film 4 is used as the insulating film. However, if the properties of the fluorine-based RIE method, such as the etching rate, do not change significantly, the multi-layer insulating film may be used. May be. For example, this insulating film is a two-layer film in which the upper and lower layers are a CVD silicon nitride film and a thin thermal oxide film, respectively. The upper layer, the intermediate layer and the lower layer are a CVD silicon oxide film, a CVD silicon nitride film and a thermal oxide film, respectively. A three-layer film, which is a silicon film, is applied.

(Embodiment 2) FIGS. 6 to 10 are cross-sectional views of processes for explaining an embodiment in which the silicon oxide film 4 in the above-described embodiment 1 is replaced with the above-described three-layer film. In these figures, the steps from FIG. 6 to FIG.
The properties of the VD silicon oxide film, the CVD silicon nitride film, and the thermal silicon oxide film with respect to the fluorine-based RIE method are not significantly different from each other. FIG.
In the shallow groove etching of the silicon layer 3 down to 0, the CVD silicon oxide film 4 having a large selectivity with silicon plays the role of an etching mask.

According to the present embodiment, a shallow groove is formed in a silicon substrate.
In the groove filling and flattening process performed after the formation of the deep groove,
The silicon nitride film 11 functions as a polishing stopper in polishing and flattening. Further, since the silicon nitride film 11 can be selectively removed using hot phosphoric acid, it is useful when exposing the silicon surface of the element formation region A. Further, the thin thermal oxide silicon film 10 under the silicon nitride film 11 relieves the stress of the silicon nitride film 11 and prevents lattice defects from entering the silicon layer 3 in the element formation region A.

(Embodiment 3) FIGS. 11 to 17 are sectional views showing the steps of a third embodiment of a method for forming a shallow groove and a deep groove in a silicon substrate according to the present invention. In this embodiment, the silicon oxide film 4 of the first embodiment is replaced with a three-layer film in which the upper layer, the intermediate layer and the lower layer are a CVD silicon oxide film, a polycrystalline silicon film and a thin thermal oxide silicon film, respectively. Is replaced by

First, as shown in FIG. 11, a high concentration impurity diffusion layer 2 and a silicon layer 3 are formed on a silicon substrate 1 as in the first embodiment. Further, a thin silicon oxide film 10 is formed on the silicon layer 3 by a thermal oxidation method, and a polycrystalline silicon film 12, a silicon oxide film 4, and a polycrystalline silicon film 5 are sequentially formed by a CVD method. Since the silicon oxide film 4 serves as a mask for etching the silicon oxide film 10 in addition to a mask for etching the shallow groove later, the silicon oxide film 4 is formed to be thicker than in the first embodiment. There is a need.

Following the formation of these films, a resist pattern 6 for forming a shallow groove covering the element formation region is formed by using a known lithography technique, and a polycrystalline silicon film is formed by chlorine-based RIE using the resist pattern 6 as a mask. 5 is etched. Since the pattern formation and the etching are performed on a flat surface, there is no problem caused by the unevenness of the base.

Next, after removing the resist pattern 6, FIG.
As shown in FIG. 2, a silicon oxide film 7 serving as a mask for deep groove etching is formed on the entire surface by a CVD method or the like, and a resist pattern 8 for forming a deep groove is formed on the silicon oxide film 7 by lithography. Since the underlying step at the time of this pattern formation is only due to the thin polycrystalline silicon film 5, there is almost no problem caused by the unevenness of the underlying layer.

Next, using the deep groove resist pattern 8 as a mask, the silicon oxide film 7 and the silicon oxide film 4 are sequentially etched by a fluorine-based RIE method, and further, as shown in FIG. 12 is etched, and the silicon oxide film 10 is again etched by the fluorine-based RIE method to expose the surface of the silicon layer 3. After that, the resist pattern 8 is removed.

At this time, if the deep groove forming region and the element forming region overlap, the polycrystalline silicon film 5 is etched by chlorine RIE between the etching of the silicon oxide film 7 and the etching of the silicon oxide film 4. Need to do. Subsequently, using the silicon oxide film 7 as a mask, the region B
The deep groove is etched. Thereafter, if necessary, a channel cut impurity diffusion layer 9 of the same conductivity type as the silicon substrate 1 is formed at the bottom of the deep groove by ion implantation.

Next, the silicon oxide film 7 is etched and removed by the fluorine-based RIE method, and as shown in FIG. 14, the silicon oxide film 4 is etched by the fluorine-based RIE method using the polycrystalline silicon film 5 as a mask. Next, as shown in FIG. 15, using the silicon oxide film 4 as a mask, the silicon film 12 is etched by a chlorine-based RIE method. At this time, the polycrystalline silicon film 5 is removed.

Subsequently, as shown in FIG. 16, the silicon oxide film 10 is etched using the silicon oxide film 4 as a mask. At this time, since the silicon oxide film 4 serving as a mask is etched at the same speed as the silicon oxide film 10, overetching after the underlying silicon layer 3 is exposed is minimized. Thereafter, using the silicon oxide film 4 as a mask, a shallow groove is etched in the region C of the silicon layer 3 by a chlorine-based RIE method as shown in FIG. 17 to obtain a structure in which the shallow groove and the deep groove are formed in the same substrate.

In the trench filling and flattening process performed after the formation of the shallow and deep trenches in the silicon substrate according to the present embodiment, the polycrystalline silicon film 12 serves as an etching stopper in the etch back flattening by the RIE method. Fulfill. Further, since the polycrystalline silicon film 12 can be selectively removed using a chlorine-based RIE method or the like, it is useful when exposing the silicon surface of the element formation region A. Further, a thin thermal oxide film 10 under the polycrystalline silicon film 12 is formed.
Prevents the silicon layer 3 in the element formation region A from being etched when the polycrystalline silicon film 12 is removed by a chlorine-based RIE method.

(Embodiment 4) FIGS. 18 to 22 are sectional views showing steps for explaining a fourth embodiment of a method for forming shallow / deep grooves in a silicon substrate according to the present invention. First, as shown in FIG. 18, a high concentration impurity diffusion layer 2 and a silicon layer 3 are formed on a silicon substrate 1 in the same manner as in the above-described embodiment. Further, a thin silicon oxide film 10 is formed on the silicon layer 3 by a thermal oxidation method, and a polycrystalline silicon film 1 is formed by a CVD method.
2. A silicon oxide film 4 and a polycrystalline silicon film 5 are sequentially formed. Subsequent to the formation of these films, a resist pattern 6 for forming a shallow groove covering the element formation region is formed by using a known lithography technique, and the polycrystalline silicon layer 5 is formed by chlorine-based RIE using the resist pattern 6 as a mask. ,
The silicon oxide film 4 is converted to a chlorine-based R by a fluorine-based RIE method.
Each of the polycrystalline silicon layers 12 is sequentially etched by the IE method.

Next, after removing the resist pattern 6, FIG.
As shown in FIG. 9, a silicon oxide film 7 serving as a mask for deep groove etching is formed on the entire surface by a CVD method or the like, and a resist pattern 8 for forming a deep groove is formed on the silicon oxide film 7 by using lithography technology. Next, as shown in FIG. 20, the silicon oxide film 7 and the silicon oxide film 10 are sequentially etched by the fluorine-based RIE method to
Expose the surface. After that, the resist pattern 8 is removed. At this time, if the deep groove formation region and the element formation region overlap, the polycrystalline silicon film 5 is interposed between the etching of the silicon oxide film 7 and the etching of the silicon oxide film 10.
Chlorine-based RIE method, fluorine-based RIE of silicon oxide film 4
It is necessary to sequentially perform the method and the chlorine-based RIE method of the polycrystalline silicon film 12. Subsequently, a deep groove is etched in the region B using the silicon oxide film 7 as a mask. Thereafter, a channel cut impurity diffusion layer 9 of the same conductivity type as that of the silicon substrate is formed at the bottom of the deep groove by ion implantation as needed.

Next, as shown in FIG.
The silicon oxide film 10 and the silicon oxide film 10 are removed by etching using a fluorine-based RIE method to expose the surface of the silicon layer 3. Thereafter, as shown in FIG. 22, a shallow groove is etched in the region C of the silicon layer 3 by chlorine-based RIE using the silicon oxide film 4 as a mask to obtain a structure in which the shallow groove and the deep groove are formed in the same substrate. Note that the polycrystalline silicon film 5 is removed during the shallow groove etching.

In this embodiment, the number of times of the RIE method is seven, which is two times smaller than that of the third embodiment, and the process is simplified. However, when the deep groove formation region and the element formation region overlap, the number of times of the RIE method is 11 times, which is the same as in the third embodiment. The formation of the deep groove resist pattern 8 in FIG. 19 and the subsequent RIE method of the silicon oxide film 7 are performed in a state where the step is larger than in the other examples (Examples 1 to 3). As long as the total thickness of the silicon oxide film 10, the polycrystalline silicon film 12, the silicon oxide film 4, and the polycrystalline silicon film 5 is not extremely large, the steps can be reduced as compared with the conventional method, and the problems associated with pattern formation and etching also occur. It is unlikely to occur.

[0037]

As described above, according to the present invention,
Since the formation of the shallow groove resist pattern and the subsequent etching are performed on a flat surface, and the formation and subsequent processing of the deep groove resist pattern are performed on a slight step, the shallow groove and the deep groove can be precisely dimensioned and freely positioned. Can be formed. As a result, an extremely excellent effect that the performance and the integration density of the silicon integrated circuit using both the shallow groove and the deep groove can be improved can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a process for explaining a first embodiment of a method for forming a shallow groove / a deep groove in a silicon substrate according to the present invention.

FIG. 2 is a sectional view of a step following FIG. 1;

FIG. 3 is a sectional view of a step following FIG. 2;

FIG. 4 is a sectional view of a step following FIG. 3;

FIG. 5 is a sectional view of a step following FIG. 4;

FIG. 6 is a cross-sectional view of a process explaining a second embodiment of the method for forming a shallow groove / deep groove in a silicon substrate according to the present invention.

FIG. 7 is a sectional view of a step following FIG. 6;

FIG. 8 is a sectional view of a step following FIG. 7;

FIG. 9 is a sectional view of a step following FIG. 8;

FIG. 10 is a sectional view of a step following FIG. 9;

FIG. 11 is a sectional view of a step for explaining a third embodiment of the method for forming a shallow groove / deep groove in a silicon substrate according to the present invention.

FIG. 12 is a sectional view of a step following FIG. 11;

FIG. 13 is a sectional view of a step following FIG. 12;

FIG. 14 is a sectional view of a step following FIG. 13;

FIG. 15 is a sectional view of a step following FIG. 14;

FIG. 16 is a sectional view of a step following FIG. 15;

FIG. 17 is a sectional view of a step following FIG. 16;

FIG. 18 is a cross-sectional view of a step for explaining a fourth embodiment of the method for forming a shallow groove / deep groove in a silicon substrate according to the present invention.

FIG. 19 is a sectional view of a step following FIG. 18;

FIG. 20 is a sectional view of a step following FIG. 19;

FIG. 21 is a sectional view of a step following FIG. 20;

FIG. 22 is a sectional view of a step following FIG. 21;

FIG. 23 is a cross-sectional view showing a configuration of a complementary MOS field effect transistor using both shallow grooves and deep grooves.

FIG. 24 is a cross-sectional view of a step illustrating a conventional method for forming a shallow groove / deep groove in a silicon substrate.

FIG. 25 is a sectional view of a step following FIG. 24;

FIG. 26 is a sectional view of a step following FIG. 25;

FIG. 27 is a sectional view of a step following FIG. 26;

FIG. 28 is a sectional view of a step following FIG. 27;

FIG. 29 is a cross-sectional view of a step explaining a conventional method for forming a shallow groove / deep groove in a silicon substrate.

FIG. 30 is a sectional view of a step following FIG. 29;

FIG. 31 is a sectional view of a step following FIG. 30;

FIG. 32 is a sectional view of a step following FIG. 31;

FIG. 33 is a sectional view of a step following FIG. 32;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... High concentration impurity diffusion layer, 3 ... Silicon layer, 4 ... Silicon oxide film, 5 ... Polycrystalline silicon film,
6: a resist pattern for forming a shallow groove, 7: a silicon oxide film,
8: Deep groove forming resist pattern, 9: Channel cut impurity diffusion layer, 10: Silicon oxide film, 11: Silicon nitride film, 12: Polycrystalline silicon film.

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3065

Claims (5)

(57) [Claims] 1. A film thinner than a depth of a shallow groove on a silicon substrate.
The has a thickness 1 of the film and the first to the first film
Forming a mask film having a thickness smaller than that of the film, leaving the mask film only in an element formation region on the silicon substrate, and forming a second film on the entire region of the silicon substrate A step of selectively removing the first film, the second film, and the mask film on the deep groove forming region of the silicon substrate; and using the remaining second film as a mask , the second film But
Forming a deep groove in the silicon substrate so as to remain ; removing a second film over the entire region of the silicon substrate; using the mask film as a mask to form a first groove in a shallow groove forming region outside an element forming region; Removing the first film, and using the remaining first film as a mask , the first film is
Forming a shallow groove in the silicon substrate so as to remain; and forming a shallow groove in the silicon substrate.
Deep groove forming method. 2. The method according to claim 1, wherein the first film is a single-layer insulating film, a two-layer film whose upper and lower layers are a silicon nitride film and a thermal silicon oxide film, respectively, or an upper layer, an intermediate layer and a lower layer film, respectively. Insulating film other than silicon nitride film,
A method for forming shallow / deep grooves in a silicon substrate, wherein the method is one of a silicon nitride film and a three-layer film of a thermal silicon oxide film. 3. The method according to claim 1, wherein the mask film is a polycrystalline silicon film. 4. A step of sequentially forming a thermal silicon oxide film, a first silicon film, a first insulating film, and a second silicon film on a silicon substrate; and forming the first silicon film only on an element formation region on the silicon substrate. 2) forming a second insulating film over the entire area of the silicon substrate; and forming the thermally oxidized silicon film, the first insulating film on the deep groove forming area of the silicon substrate. Selectively removing a second insulating film, the first silicon film, and the second silicon film; forming a deep trench in a silicon substrate using the remaining second insulating film as a mask; Removing the second insulating film over the entire area of the silicon substrate;
Removing the first insulating film in the shallow groove forming region outside the element forming region using the second silicon film as a mask; forming a shallow groove outside the element forming region using the remaining first insulating film as a mask A step of removing the first silicon film and the thermally oxidized silicon film on a region; and a step of forming a shallow groove in a silicon substrate using the first insulating film as a mask. A method for forming shallow and deep grooves in a substrate. 5. A step of sequentially forming a thermal silicon oxide film, a first silicon film, a first insulating film, and a second silicon film on a silicon substrate; and forming the first silicon film only on an element formation region on the silicon substrate. Leaving a first insulating film, a first silicon film, and a second silicon film; forming a second insulating film on the entire region on the silicon substrate; and forming a deep groove on the silicon substrate. Selectively removing the thermally oxidized silicon film, the first insulating film, the second insulating film, and the first and second silicon films, and masking the remaining second insulating film. Forming a deep groove in the silicon substrate, removing the second insulating film and the thermally oxidized silicon film on the entire region of the silicon substrate, and removing the remaining first insulating film as a mask in the silicon substrate. Shallow groove Forming a shallow groove / deep groove in a silicon substrate.