JPH0230160A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a floating capacitance between a wiring layer and a silicon substrate, and obtain a semiconductor device having a high integration degree and capable of high speed operation, by arranging, in a field region, a silicon oxide film which is formed in the self-matching manner in the range of width of an isolation trench, and has a thickness larger than insulating films on an element region. CONSTITUTION:On the surface of a semiconductor substrate 1 in the title device, an element region B and a field region A are formed and isolated by an isolation trench 4 whose inside is filled with polycrystalline silicon. A silicon oxide film 10 is formed in the field region A, in the self-matching manner in the range of width of the isolation trench 4, and the thickness is larger than the thicknesses of insulating films 2, 3 on the element region B. For example, after the silicon oxide film 2 is formed on the silicon substrate 1, and the silicon nitride film 3 is deposited, the trench 4 is formed and then a channel stopper layer 5 is formed. A silicon oxide film 6 is formed on the side surface and the bottom surface of the trench 4, and the inside of the trench is filled with polycrystalline silicon 7. After that, oxidizing is performed by using the silicon nitride film 3 as a mask, and the thick silicon oxide film 10 is formed on the upper part of the polycrystalline silicon 7 and on the field region A.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and more particularly to a highly integrated semiconductor device that uses isolation between elements by deep trenches filled with polycrystalline silicon.

[Conventional technology]

Inter-element insulation isolation using deep isolation trenches does not cause the oxidized film to dig into the active region, which is called birthbeak, which occurs in normal selective oxidation methods, so the area required for insulation isolation is smaller than in selective oxidation methods, resulting in high efficiency. This method is advantageous as an insulation isolation method for highly integrated semiconductor integrated circuit devices.

Conventionally, when insulation isolation between elements is performed using an isolation trench, the type and thickness of the insulating film formed on the surface of the element formation region surrounded by the isolation trench and the region outside the isolation trench where no element is formed are the same structure. It became.

[Problem to be solved by the invention]

In the conventional groove isolation structure described above, the same insulating film is formed at the same thickness above the field region as on the region where the element is formed, so it is not possible to obtain an insulating film of sufficient thickness. Therefore, a considerable amount of stray capacitance occurs between the metal wiring layer formed further above and the semiconductor substrate, which has the drawback of hindering high-speed operation of the device.

In order to avoid this, we use a combination of insulation isolation using trenches and oxide film isolation using selective oxidation, and use oxide film isolation in areas where there is a wide field area as a result of the arrangement of elements, and in areas where elements are closely arranged. Using trench isolation is an effective method, but not only does the process for isolation become extremely complicated, but the photolithography process that is performed in the subsequent process to form the device requires the use of isolation trenches and isolation oxidation. Since alignment is performed on both sides of the film at the same time, there is a constraint that the relative positions of the isolation trench and the isolation oxide film must be precisely aligned in advance. It is not desirable to use two types of isolation methods together.

[Means to solve the problem]

The present invention provides a semiconductor device in which an element region and a field region are separated from each other by an isolation trench filled with polycrystalline silicon on the surface of a semiconductor substrate, in which an element region and a field region are formed in a self-aligned manner within the width of the isolation trench. and has a silicon oxide film thicker than the thickness of the insulating film on the element region.

〔Example〕

Next, two embodiments of the present invention will be described with reference to the drawings.

[Example 1] As a first example, a vertical cross-sectional view of the structure is shown in FIG. 1(c). The inner wall of the isolation trench has a thin oxide film buried in polycrystalline silicon 7, and the surface of region B (element formation region) has a silicon oxide film 2 and a silicon nitride film 3 thereon.
There is a thick (5000 Å or more) silicon oxide film 10 on the surface of region A (region where no element is formed).

Next, this manufacturing method will be explained based on FIG. 1. As shown in FIG. 1(a), a first silicon oxide film 2 of 500 layers is formed by oxidizing the main surface of a P-type silicon substrate 1, and a silicon nitride film 3 of 1000 layers is formed by vapor phase growth. After depositing the silicon nitride film 3, the first silicon oxide film 2, and the silicon substrate 1 by anisotropic dry etching using the photoresist pattern as a mask, the silicon nitride film 3, first silicon oxide film 2, and silicon substrate 1 are sequentially etched to a width of 1.
A groove 4 of 5 μm and 4 μm deep is formed. B at the bottom of groove 4
After + ions are implanted to form a P+ channel stopper layer 5, the photoresist material is removed. Here, the region A divided by the groove 4 is a field region in which no element is formed, and the region B
is the active region forming the device. Next, (b) in Figure 1
As shown in FIG. 3, a second silicon oxide film 6 with a thickness of 2,000 thick is formed on the side and bottom surfaces of the trench 4 by oxidation using the silicon nitride film 3 as a mask, and the inside of the tg4 is filled with polycrystalline silicon 7. Oxidation is performed again using the silicon nitride film 3 as a mask to form a third silicon oxide film 8 on the surface of the polycrystalline silicon 7.

Next, a photoresist pattern 9 is formed to remove the silicon nitride film 3 on the field region, and plasma etching is performed to remove the exposed silicon nitride film 3. Next, as shown in FIG. 1(c), the photoresist material 9
After removing the silicon nitride film 3, oxidation is performed using the silicon nitride film 3 as a mask to form a fourth silicon oxide film 10 having a thickness of 6,000 wafers on the top of the polycrystalline silicon 7 and on the field region, thereby completing an insulating isolation region. After this, elements are formed in the active region B, and a metal wiring layer is formed to connect the elements.

In this embodiment, by leaving the silicon nitride film pattern formed by etching the groove 4 only on the active region, the fourth silicon oxide film 10 is formed in a self-aligned manner with respect to the groove.

[Example 2] As a second example, a longitudinal sectional view of the structure is shown in FIG. 2(c). The inner wall of the isolation trench has a silicon oxide film 11 on which a silicon nitride film is buried and is buried in polycrystalline silicon 7, and the surface of region B (element formation region) has a silicon oxide film 11 and a silicon nitride film 3 thereon. There is a thick (5000 Å or more) silicon oxide film 14 on the surface of region A (region where no element is formed).

Next, this manufacturing method will be explained with reference to FIG. As shown in FIG. 2(a), a groove 4 with a width of 1.5 μm and a depth of 4.0 μm is etched into a P-type silicon substrate 1 by anisotropic dry etching, and B+ ions are implanted into the bottom of the groove to form a P+ channel. A stopper layer 5 is formed. Next, as shown in FIG. 2(b), first silicon oxide films 11 and 100 with a film thickness of 500 are coated on the surface of the silicon substrate I and the side and bottom surfaces of the trench 4.
0 silicon nitride films 12 are sequentially formed. The inside of the groove 4 is filled with polycrystalline silicon 7, and the surface of the polycrystalline silicon 7 is oxidized to form a second silicon oxide film 13 with a thickness of 1000.
After forming, the silicon nitride film 12 on the field region is removed using the photoresist pattern 9 as a mask as in the first embodiment. Next, as shown in Figure 2(c),
Using the silicon nitride film 12 left on the active region as a mask, oxidation is performed to obtain a third silicon oxide film 14 with a thickness of 6000 nm over the polycrystalline silicon 7 and on the field region.

Here, the third silicon oxide film, which is a field oxide film, is obtained in a self-aligned manner with respect to the trench 4, as in the first embodiment. Further, in the second embodiment, since the side surfaces of the trench are covered with a silicon nitride film, even if the field region is oxidized thickly, the oxidation does not penetrate into the active region at all.

〔Effect of the invention〕

As explained above, the present invention enables isolation between wiring layers and silicon substrate by forming a silicon oxide film with a thickness of 5000 Å or more on the surface of the silicon substrate in the field region where no elements are formed, when performing insulation isolation using deep trenches. It is possible to reduce the stray capacitance between the semiconductor devices and realize a semiconductor device that is highly integrated and capable of high-speed operation.

[Brief explanation of the drawing]

FIG. 1(c) is a longitudinal cross-sectional view of the first embodiment of the present invention, and (a) to (c) are longitudinal cross-sectional views in main steps,
FIG. 2(c) is a longitudinal cross-sectional view of a second embodiment of the present invention, and (a) to (c) thereof are longitudinal cross-sectional views in main steps. 1... P-type silicon substrate, 2... First
silicon oxide film, 3...silicon nitride film, 4
...Separation trench, 5...P'' channel stop layer 6...Second silicon oxide film, 7...
... Polycrystalline silicon, 8 ... Third silicon oxide film, 9 ... Photoresist, 10 ...
- Fourth silicon oxide film, 11... First silicon oxide film, 12... Silicon nitride film, 13.
...Second silicon M ([,14...Third silicon oxide film, A...Field region,
B...Active region.

Claims (1)

[Claims] In a semiconductor device in which an element region and a field region are separated from each other by an isolation trench filled with polycrystalline silicon on the surface of a semiconductor substrate, the field region is formed in a self-aligned manner within the width of the isolation trench; A semiconductor device comprising a silicon oxide film that is thicker than an insulating film on an element region.