JPS6060736A - Manufacture of semicondutor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize a semiconductor integrated circuit device, wherein the width of each interelement isolating region is narrow and there is little parasitic capacity, by a method wherein, after the surface of the substrate was oxidized using an oxidation-resistant film formed selectively on the substrate as a mask, grooves are formed in parts of the substrate with a fixed width on the periphery of the oxidation-resistant film and the grooves are filled with an oxide film. CONSTITUTION:A first oxidation-resistant film 4 is selectively formed on the main surface of a substrate 1, whereon a diffusion layer 2 and an epitaxial layer 3 having been formed, and moreover, a CVD oxide film 5 is formed on the film 4 excluding parts of the film 4 with a fixed width on the periphery of the film 4. Then, after a thermal oxide film 7 was formed on the surface of the substrate 1, parts of the film 4, where have not been covered with the film 5, are removed and grooves 8 are formed there. A thin oxide film is respectively formed on the inner walls of the grooves 8 and after ions were implanted in the bottom parts of the grooves 8, a silicon nitride film 13 is formed on the whole surface including the surfaces of the inner walls of the grooves 8. A CVD oxide film 14 is deposited on the whole surface of the film 13 and after the grooves 8 were filled, the film 14 is removed, being left the film 14 only in the grooves 8 intact.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and particularly to a method of forming an element isolation region suitable for a bipolar semiconductor integrated circuit device.

(Conventional technology) Element isolation for bipolar semiconductor integrated circuit devices.

In the past, the PN junction isolation method was used, but as devices become smaller and the degree of integration increases, it becomes necessary to reduce the area of the isolation region, so an oxide film isolation method that uses a thick silicon oxide film by selective oxidation of the silicon substrate has been adopted. (so-called isoplanar).

The oxide film isolation method not only significantly reduces the isolation area compared to the PN isolation method, but also eliminates all areas other than the element area (
This is an effective method that reduces the stray capacitance between the wiring and the substrate and contributes to speeding up since the area (hereinafter referred to as a field region) is converted into a thick oxide film.

In the oxide film isolation method, the electron formation region is covered with an oxidation-resistant mask such as a two-layer film consisting of a silicon nitride film laminated on a thin silicon oxide film, and the volume is increased by oxidation in the region where a thick oxide film is to be formed. In order to prevent this, a groove is formed by etching and then thermally oxidized to make the element region and the isolation region into substantially flat surfaces.

Therefore, oxidation progresses in the side direction of the groove, and the width of the separation region is always wider than the width defined by photoetching.
Considering the margin for mask alignment with the buried diffusion layer, the limit is about 10 μm.

Furthermore, between the silicon substrate in the element region and the oxidation-resistant mask layer, an oxide film extending in a wedge shape from the isolation region,
That is, there is a drawback that a perfectly flat surface cannot be obtained due to the formation of perspective peaks and the formation of a raised oxide film, that is, a bird's head, around the device region.

On the other hand, the miniaturization of elements has progressed further, and it has become necessary to further reduce the area of isolation regions in order to achieve higher integration.

HVC is an anisotropic etching technique that etches the film perpendicular to the substrate surface.
RIE (hereinafter referred to as RIE) has been put into practical use, and new device isolation methods are being developed to replace oxide film isolation methods.

The various new separation techniques that have been proposed can be broadly classified into the following two categories.

One is to dig a deep trench by RIE and flatten it by backfilling it with silicon dioxide or polycrystalline silicon (hereinafter referred to as the trenching method). First, the sidewalls of the trench are also covered with an oxidation-resistant mask layer to prevent the increase in isolation region width and the formation of park peaks and bird's heads due to lateral oxidation (hereinafter referred to as improved selective oxidation method). It is.

In the trenching method, after forming a trench, an insulating material such as silicon dioxide or an insulating film is formed on the inner wall of the trench, and then polycrystalline silicon or the like is deposited thickly, and the trench is flattened by etch-packing. When applied to a bipolar semiconductor integrated circuit device, there is an advantage that a deep groove penetrating the buried diffusion layer formed on the entire surface of the substrate can be formed and a mask for buried diffusion can be omitted; It is difficult to planarize narrow grooves and wide field area grooves at the same time, which requires a planarization mask, requires strict alignment accuracy, and complicates the process. There are drawbacks.

On the other hand, with the improved selective saponification method, flattening is possible regardless of the separation width, and the process is relatively simple, but separation through the buried diffusion layer is practically impossible, so A mask is required, and as the isolation region becomes narrower, the accuracy of mask alignment for buried diffusion and isolation becomes more difficult, so the trenching method cannot reduce the width of the isolation region. Also, the P layer for channel stop provided directly under the selective oxide film contacts the N buried layer.

The disadvantage is that the parasitic mass is larger than that of the Mizohori method.

Furthermore, since there is little lateral oxidation, the two channel stop layers spread outside the diffusion isolation oxide film, which may cause leaks and a drop in breakdown voltage.

(Object of the Invention) The present invention was made in view of the drawbacks of Towara, and it is possible to form a flat surface regardless of the width of the isolation region by just one photolithography process, and It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device that can reduce the width, reduce parasitic capacitance, and omit a buried diffusion mask when applied to a bipolar type.

(Part 4 of the Invention) The method for manufacturing a semiconductor integrated circuit device of the present invention includes selectively forming an oxidation-resistant first film on the main surface of a semiconductor substrate, and forming a constant width around the periphery of the first film. A step of forming a second film on the first film except for region 1 using an etching mask of this film, and a step of converting the main surface that is not covered with the first film into an oxide film. , removing the first film that is not covered with the second film to expose the main surface of the substrate; forming a groove in the exposed substrate with sidewalls substantially perpendicular to the main surface of the substrate; a step of forming an oxidation-resistant third film on the entire main surface including the inner wall of the trench; a step of depositing a fourth film on the third film and filling the trench with the fourth film; removing the fourth film until the oxide film and the third film on the second film are exposed; removing the exposed third film and then removing the oxide film; a step of exposing the main surface of the substrate immediately below the film; a step of etching the polished main surface of the substrate or the exposed main surface of the substrate and the fourth film surface in the groove to a predetermined thickness; The method is characterized by comprising a step of oxidizing the thinned surface until it becomes approximately at the same height as the surface of the substrate immediately below the first film.

Further, in the method of manufacturing a semiconductor integrated circuit device of the present invention, an oxidation-resistant first film is selectively formed on the main surface of a semiconductor substrate, and the first film is formed on the main surface of the semiconductor substrate except on a region of constant +1 Vif around the first film. forming a second film on the first film to serve as an etching mask for this film; converting the main surface not covered with the first film into an oxide film; removing the first film to expose the main surface of the substrate; forming a groove in the exposed substrate with side walls substantially perpendicular to the main surface of the substrate; a main surface including the inner wall of the groove; a step of forming an oxidation-resistant third film on the entire surface, removing the remaining part of the film so as to leave the third film and the first film on the side walls of the trench, and partially forming the semiconductor substrate; a step of depositing a fourth film on the entire surface including the exposed substrate and filling the structure with the fourth film; a step of etching the fourth film and the main surface of the substrate directly under the fourth film so that more than half of the fourth film remains; , ? !
It is characterized by having a step of oxidizing until the height becomes the same.

(Example) Embodiments of the present invention will be explained below with reference to the drawings.

In the embodiment, the present invention is applied to a bipolar type semi-loose 1-volume circuit device, but the scope of application of the present invention is not limited to this, and can be applied to MOS type and other semiconductor integrated circuit devices. is also possible.

FIGS. 1(A) to 1(I) are process cross-sectional views showing a first embodiment of the present invention.

In FIG. 1(A), 1 is a P-type silicon substrate, 2 is an N''-type buried diffusion layer formed on the substrate 1, and 3 is an N-type epitaxial layer formed on the diffusion layer 2. Hereinafter, these substrate 1 and layers 2 and 3 will be collectively referred to as a silicon substrate (semiconductor substrate).

As shown in FIG. 1(A), a first oxidation-resistant film (first film) 4 and a CVD oxide film (
A second film) 5 is sequentially deposited. Here, the first oxidation-resistant film 4 is desirably a two-layer film in which a silicon nitride film with a thickness of 1000 to 3000 times is laminated on a thin thermal oxide film of, for example, 300 to 1000 times.

Next, as shown in FIG. 1, the CVD oxide film 5 is etched using the resist layer 6 as a mask by a conventional photolithography method.

At this time, side etching of approximately 0.5 to 2 μm is performed, for example. This side etching can be performed with high precision using, for example, a hydrofluoric acid-ammonium fluoride aqueous solution.

Subsequently, as shown in FIG. 1C, the first oxidation-resistant film 4 is vertically etched by RIE using the resist layer 6 as a mask. As a result, the first oxidation resistant [4] is formed on the selected main surface of the silicon substrate, and furthermore, the c V D oxide film 5 is formed on the periphery of the 10th oxidized film 4 with a constant width. It is formed on the first copper oxide film 4 except on the region.

Note that in order to obtain the shape shown in FIG. You may also perform sex.

Next, after removing the resist layer 6, the exposed surface of the silicon substrate (the portion not covered with the first oxidation-resistant film 4) is thermally oxidized to form a surface as shown in FIG. 1(D). A thermal oxide film 7 with a thickness of about 0 tW is formed as shown in FIG.

After that, using the thermal oxide film 7 and the CVD oxide film 5 as a mask,
The portions of the first oxidation-resistant film 4 that are not covered with the CVD oxide film 5 are removed to expose the silicon substrate in those portions.

Thereafter, a groove 8 is formed in the exposed portion of the silicon substrate as shown in FIG. 1(6). Here, trench 8 is formed by RIE so as to penetrate epitaxial layer 3 and buried diffusion layer 2 and reach silicon substrate 1, and to have sidewalls substantially perpendicular to the main surface of the silicon substrate. In addition, in the said FIG. 1 (G) which shows the state in which this groove 8 was formed,
CV D Aj? The portion of the silicon substrate covered with the oxide film 5 and the first oxidation-resistant film 4 is placed in the element formation region 9. , 92. Further, the space between the element formation regions 9I and 92 is defined as an element isolation region 1o. Further, the peripheral portion is made into a wide field region 11.

Subsequently, by thermal oxidation, the inner wall of the groove 8 is coated with 200 to 1000
Form an oxide film as thin as A. Next, depending on the impurity concentration of the p-type silicon substrate, a P-type impurity is ion-implanted into the bottom of the fII8 as necessary to form a channel stop (N-type inversion layer) as shown in FIG. Form a P-type layer 12 (for prevention of occurrence). After that, a silicon nitride film (hereinafter referred to as a second oxidation-resistant film) 13 with a thickness of about 500 to 2000 mm is applied as a third film to the entire surface including the inner wall of the groove 8 cut with the thin oxide film. It is formed as shown in FIG. In FIG. 1(G), on the inner surface of the groove 8, the second layer including the thin oxide film is shown as oxidizing Hg 13. Thereafter, a CVD oxide film (fourth film) 14 is thickly deposited on the entire surface of the second oxidation-resistant film 13, and the groove 8 is filled with the CVD oxide film 14 as shown in the first drawing.

Subsequently, the CVD oxide film 14 is etched and packed until the second oxidation-resistant film 13 on the thermal oxide film 7 and the CVD 9 film 5 is exposed, and the CVD oxide film 14 is grooved as shown in FIG. Leave only within 8.

Thereafter, the second oxidation-resistant film 13 exposed on the flat surface and the CVD oxide film 5 and thermal oxide film 7 thereunder are removed in a self-aligned manner. Then, as shown in FIG. 1I, the silicon substrate stretched out by removing the thermal oxide film 7 is etched to a surface approximately 0.5 to 2 μm lower than the surface of the silicon substrate in the element region 9I.

Next, thermal oxidation is performed. This thermal oxidation causes the
As shown in FIG. 2, a thick thermal oxide film 15 of about 1 to 4 μm is formed on the exposed silicon substrate of the element isolation region 10 and the field region 11, and due to the increase in volume at that time, the rounded surface becomes the first layer. It becomes flat with the main surface of the substrate directly under the oxidation-resistant film 4. Due to the heat treatment at this time, the C buried in the groove 8
The VD oxide film 14 becomes dense and has almost the same quality as a thermal oxide film.

After that, element region 9. , 92 first FM oxidizing film 4
is removed to form the element region 9. , 92 to form a semiconductor integrated circuit device. In FIG. 1(G), the film 14 is made of polycrystalline silicon,
0, the polycrystalline silicon in the groove 8 may be etched at the same time as the silicon substrate is etched, and the surface of the polycrystalline silicon may be oxidized simultaneously with the oxidation of the silicon substrate in FIG. 1(I). In this case, a homogeneous thick oxide film is formed on the polycrystalline silicon in the groove 8 at the same time as the thick thermal oxide film 15 on the silicon substrate.

As explained above, according to the first embodiment of the present invention, element isolation with a flattened surface without dependence on the isolation region width is possible with only one photolithography process. Since a separate mask is not required, the problem of mask alignment accuracy is solved. In addition, the element formation region 9. , 92 can be formed with an extremely narrow and deep isolation groove 8, so that a mask for buried diffusion can also be omitted.

Furthermore, the width of the inter-element isolation region 10 can also be reduced to about 3 to 5 μm using ordinary photolithography using ultraviolet light, which is 1/2 that of the conventional isoplanar method.
It can be reduced to ~1/3, and no thermal bird's beak or bird's head occurs.

Further, the buried diffusion layer 2 does not expand laterally inward with respect to the element forming regions 90, 9□, and furthermore, the channel stop P
Since the mold layer 12 and the buried diffusion layer 2 are completely separated,
The parasitic capacitance between the element region and the substrate is extremely small, and since the field region 11 is covered with an extremely thick thermal oxide film 15, the capacitance between the wiring formed thereon and the substrate is also small, resulting in lower power consumption and The structure is suitable for high speed.

Further, the CVD oxide film 14 buried in the trench 8 is densified by the heat treatment when forming the thick thermal oxide film 15 in the field region 11, and has almost the same quality as the thermal oxide film, or the film 14 is If polycrystalline silicon is used, a thermal oxide film with exactly the same quality as that on the silicon substrate in the field region is formed on the polycrystalline silicon, so self-alignment technology is actively used in the subsequent device formation process. be able to.

FIG. 2 is a process sectional view showing a second embodiment of the present invention. In this second embodiment, the steps up to step 8 in FIG. 1(g) are the same as those in the first embodiment.

In the second embodiment, following the step in FIG.
The oxide film 5 and the thermal oxide film 7 may be left without being removed),
A thin thermal oxide film is formed on the exposed surface of the silicon substrate including the inner wall of the groove 8, and then a silicon nitride film is deposited on the entire surface including the inner wall of the groove 8. This thermal oxide film and nitride film are combined to form a second oxidation-resistant film 13.

After that, etching using RIE is performed. Then, as shown in FIG. 2(5), the first oxidation-resistant film 4 on the element formation region and the second oxidation-resistant film 13 on the inner wall of @S remain.
The other oxide films and nitride films are removed to expose the silicon substrate. Next, polycrystalline silicon (fourth film) 16 is applied to the entire surface including the exposed substrate as shown in FIG. and fill 18 with polycrystalline silicon 16.

Next, the polycrystalline silicon 16 is etched back, and as shown in FIG.
As shown in 3), the surface of the polycrystalline silicon 16 is 1 of the depth of the groove 8.
Make sure that the depth is at an appropriate depth, not exceeding /2. At this time,
In the element formation regions 91 p 92, the first oxidation-resistant film 4
Etching stops when etching is completed, but in regions other than the trenches of the element isolation region 1o and the field region 11, the silicon substrate is etched following the polycrystalline silicon 16, and the surface becomes the same as the surface of the polycrystalline silicon 16 in the trench 8. And #Okaho Dosato becomes Sato.

Next, as shown in FIG. 2(C), the silicon substrate and polycrystalline silicon 16 are thermally oxidized to form a thick thermal oxide film 15 on the surface, and the hollowed surface is directly under the first oxidation-resistant film 4. Make it flat with the substrate surface.

In the second embodiment described above, exactly the same effect as in the first embodiment can be obtained, and furthermore, in this example, since the groove bottom and the base are St-St, no reversal occurs in the N type. ,
There is no need for a P+ layer for channel stop, and the etch pack of polycrystalline silicon 16 and the etching of the silicon substrate can be performed continuously, so the process can be shortened compared to the first embodiment. There are advantages.

(Effects of the Invention) As is clear from the above embodiments, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, the structure described above provides a flat surface and a width of the isolation region. Dependency-free element isolation is made possible by a single photolithography process, and the area of the isolation region can be significantly reduced.
Furthermore, the parasitic violet is /J% smaller, and when applied to a bipolar type, the buried diffusion mask can be omitted. The method of the present invention can be widely applied to methods of manufacturing various highly integrated and high-performance semiconductor integrated circuit devices including bipolar type devices.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view for explaining a first embodiment of the method for manufacturing a semiconductor integrated circuit device of the present invention, and FIG. 2 is a process sectional view for explaining a second embodiment of the invention. be. 1... P1 silicon substrate, 2... a mold buried diffusion layer,
3... N-type epitaxial layer, 4... First sake ^
oxidation film, 5...CVD oxide film, 6...resist layer,'l...thermal oxide film, 8...groove, 13...second oxidation resistant film, 14... -CVDM film, 15...thermal oxide film, 16...polycrystalline silicon. Patent Applicant Oki 1 ni Ki Kogyo Co., Ltd. Procedural Amendments January 18, 1949 4.1 Mr. Kazuo Wakasugi, Commissioner of the Japan Patent Office 1, Indication of the Case 1982 Patent Application No. 168267 2, Invention Name: Manufacturing method for semiconductor integrated circuit devices 3, Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 5, Date of amendment order Showa year, month, day (self-motivated) (1
) On page 6 of the specification, lines 3 and 4, "after forming RFT" should be corrected to "after forming".

Claims (2)

[Claims] (1) An oxidation-resistant first film is selectively formed on the main surface of the semiconductor substrate, and an etching mask for this film is formed on the first film except for a region of a constant width around the first film. a step of converting the main surface not covered with the first film into an oxide film; and a step of removing the first film not covered with the second film to form a main surface of the substrate. a step of exposing the surface; a step of forming a groove in the exposed substrate with side walls substantially perpendicular to the main surface of the substrate; and forming an oxidation-resistant third film on the entire main surface including the inner wall of the groove. Step #Depositing a fourth film on the third film and filling the trench with the fourth film, depositing the fourth film on the third film until the oxide film and the third film on the second film are exposed. a step of removing the exposed third film, further removing the oxide film, and exposing the main surface of the substrate immediately below the oxide film;
A step of etching the exposed main surface of the substrate, or the exposed main surface of the substrate and the fourth film surface in the groove to a predetermined thickness, A method for manufacturing a semiconductor integrated circuit device, comprising the step of oxidizing the substrate until the substrate surface is approximately at the same height as the surface of the substrate. (2) An oxidation-resistant first film is selectively formed on the main surface of the semiconductor substrate, and an etching mask for this film is formed on the first film except for a region of a constant width around the first film. forming a second film, converting the main surface not covered with the first film into an oxide film, removing the first film not covered with the second film to form a second film on the substrate; a step of exposing the main surface, a step of forming a groove in the exposed substrate with a side wall substantially perpendicular to the main surface of the substrate, and a step of forming an oxidation-resistant third film on the entire main surface including the inner wall of the sieve. a step of partially exposing the semiconductor substrate by removing the remaining portion of the film so as to leave the third film and the first film on the side wall of the groove, the step of partially exposing the semiconductor substrate; a step of depositing a fourth film on the entire surface and filling the trench with the fourth film; depositing the fourth film in the trench so that more than half of the depth of the trench remains; and a step of etching the main surface of the substrate directly under the fourth film, and a step of oxidizing the surface depressed by this etching until it has almost the same texture as the surface of the substrate directly under the first film. A method for manufacturing a semiconductor integrated circuit device characterized by: