JPH05291395A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To form an element isolation region of a semiconductor so that an element forming region may have the same dimensions as designed values and a stress may not generate inside a substrate. CONSTITUTION:A side wall 11 is formed in a groove 3 forming an element isolation and used as a mask, and a thermal oxide layer is formed inside a substrate by thermal oxidizing, and this thermal oxide layer is removed by etching. Thereafter, the side wall 11 is used again as a mask to form a thermal oxide layer 13 inside the substrate by thermal-oxidizing so that an element forming region may be insular or in a state near to an island. Accordingly, the side wall can prevent an expansion of a groove width at thermal-oxidizing and the width of an element isolation region can be formed to measure with good controllability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, it has good controllability of an element isolation region for isolating an element formation region into an island shape or a state close to an island shape, and does not contain stress in the substrate. The present invention relates to a method of manufacturing a semiconductor device that can be formed as described above.

[0002]

2. Description of the Related Art FIG. 13 is a sectional process view showing a conventional method for manufacturing a semiconductor device in which an element formation region is separated into an island shape or a state close to an island shape by an oxide layer using accelerated oxidation. In the figure, 1 is a semiconductor substrate made of a single crystal (hereinafter referred to as a substrate), 2 is a high concentration impurity layer formed in the substrate 1, 3
Is a groove that is a recess formed in the substrate 1, 4 is a gate insulating film, 5 is a gate electrode, 6 is a thermal oxide layer, and 7 is an element formation region.

Next, a conventional manufacturing method will be described. First, as shown in FIG. 13A, a groove 3 reaching at least a part of the high-concentration impurity layer 2 is formed by etching on the semiconductor substrate 1 of the first conductivity type in which the high-concentration impurity layer 2 is formed. To do.

Next, as shown in FIG. 13B, a thermal oxide layer 6 is formed by a thermal diffusion method so that the element forming region 7 has an island shape or a shape close to an island shape. In this case, since the high-concentration impurity layer 2 has a higher oxidation rate than the substrate 1, the thermal oxide layer 6 is formed along the high-concentration impurity layer 2.

After that, as shown in FIG. 13C, the thermal oxide layer 6 is etched until the surface of the element forming region 7 is exposed to form a gate insulating film 4 and a gate electrode 5.

According to the procedure described above, the element isolation region is formed so that the element formation region 7 of the semiconductor device has an island shape or a shape close to an island shape.

[0007]

As described above, in the conventional method for manufacturing a semiconductor device, the trench 3 is formed by etching, and then the thermal oxide layer 6 is formed by using the thermal diffusion method. Since the area was formed, for example, FIG.
As shown in (a) and (b), when the width of the groove 3 formed by etching is a and the thickness of the thermal oxide layer formed by thermal diffusion on the side wall of the groove 3 is b, the finally formed element The width of the isolation region is (a + 2b), which is largely influenced by the thickness of the thermal oxide layer whose dimension control is poor, and cannot be controlled according to the dimension, and the element formation region 7 becomes small, which is suitable for a highly integrated semiconductor device. There was a problem that I could not.

Further, there is a problem that the region where the high-concentration impurity layer 2 is thermally oxidized causes stress inside the substrate due to an increase in volume thereof, which adversely affects device characteristics.

The present invention has been made to solve the above-mentioned problems, and it is possible to form an element isolation region so as not to generate stress inside the substrate, and to control the element isolation width according to a dimension. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be sufficiently applied to an integrated semiconductor device.

[0010]

According to a method of manufacturing a semiconductor device according to the present invention, a groove reaching a high-concentration impurity layer formed in a semiconductor substrate is formed in an element isolation region, and then a first oxide is formed at the bottom of the groove. A layer is provided, and then sidewalls are provided on both side walls of the groove, a second oxide layer is formed at the bottom of the groove by thermal oxidation using the sidewall as a mask, and the second oxide layer is removed by etching. A third oxide layer is formed again in the removed portion of the second oxide layer by thermal oxidation to form an element formation region in an island shape or a shape close to an island shape, and then the sidewall is removed. is there.

Further, in the method for manufacturing a semiconductor device according to the present invention, after forming a groove reaching the high concentration impurity layer formed in the semiconductor substrate in the element isolation region, a first oxide layer is provided at the bottom of the groove, Then, sidewalls are provided on both side walls of the groove, a second oxide layer is formed at the bottom of the groove by thermal oxidation using the sidewall as a mask, and the second oxide layer is removed by etching, and then the second oxide layer is removed. A third oxide layer is again formed in the oxide layer removal portion by thermal oxidation to form an element formation region in an island shape or a shape close to an island shape, then the sidewalls are removed, and the fourth groove is formed in the middle of the groove. After the oxide layer is provided, the transistor is formed so as to bite into a part of the side surface of the element formation region.

[0012]

According to the method of manufacturing a semiconductor device of the present invention, the first oxide layer is formed at the bottom of the groove for forming the element isolation, the sidewall is formed on the side wall of the groove, and then the first oxide layer is formed by thermal oxidation. Since the second and third oxide layers are formed, the stress inside the substrate can be removed, and the width of the element isolation region does not widen during the thermal oxidation. It can be formed with good control.

Further, according to the method of manufacturing a semiconductor device of the present invention, after the first oxide layer is formed on the bottom of the groove for forming the element isolation, the sidewall is formed on the side wall of the groove and then the thermal oxidation is performed. To form the island-shaped or island-shaped near the element formation region, after removing the sidewalls, after providing the fourth oxide layer to the middle of the groove, Since the transistor is formed so as to dig into part of the side surface of the element formation region, the stress inside the substrate can be removed, and the width of the element isolation region does not expand during thermal oxidation. The element isolation width of the region can be formed with good control according to the dimension. Further, the channel formation region of the transistor extends to part of the side surface of the groove of the element isolation region, the effective channel width is widened, and the shape of the channel formation region is large. Bend , The depletion layer is less likely to spread, it is possible to suppress the narrow channel effect.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 11 are cross-sectional views of main steps showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

In these figures, 1 is a semiconductor substrate, 2 is
Is a high concentration impurity layer formed in the substrate 1, 3 is a groove which is a recess formed in the substrate 1, 4 is a gate insulating film, 5 is a gate electrode, 7 is an element formation region, 10 is a first oxide layer , 11
Is a sidewall, 12 is a second thermal oxide layer, and 13 is a third
Is a thermal oxide layer, and 14 is a fourth oxide layer.

The manufacturing method of this embodiment will be described below with reference to FIGS. First, in FIG. 1, a groove 3 having a width a reaching at least a part of the high concentration impurity layer 2 by etching is formed on a first conductivity type semiconductor substrate 1 in which the high concentration impurity layer 2 is formed as in the conventional example. To form.

Next, as shown in FIG. 2, a first oxide layer 10 is formed by the CVD method so as to fill the groove 3.

Then, as shown in FIG. 3, the first oxide layer 10 is etched by dry etching so that only the bottom of the groove 3 is left.

Next, in order to prevent the oxidation of the substrate 1, C
A nitride film is formed on the entire surface by the VD method, and anisotropic etching is performed to form sidewalls 11 only on the sidewalls of the trench 3 as shown in FIG.

Then, as shown in FIG. 5, a second thermal oxide layer 12 is formed by a thermal diffusion method. At this time, the second thermal oxide layer 12 is not formed in the formation portion of the sidewall 11. Here, the thick second thermal oxide layer 12 is formed by the thermal diffusion method.
When the film is formed, stress is generated inside the substrate due to the increase in volume. In this embodiment, in order to remove this stress, as shown in FIG.
Only the thermal oxide layer 12 of is selectively removed.

Then, a third thermal oxide layer 13 is formed by a thermal diffusion method until the element forming region 7 shown in FIG. 7 has a shape close to an island shape. At this time, since the space is formed inside the substrate by removing the second thermal oxide layer 12, the volume increase due to the formation of the thermal oxide layer 13 is absorbed in this space, and the stress inside the substrate does not occur.

Next, as shown in FIG. 8, only the side wall 11 is removed by selective etching.

Then, as shown in FIG. 9, a fourth oxide layer 14 for filling the groove 3 is formed by the CVD method,
As shown in 0, etching is performed until the surface of the element forming region 7 appears. Here, in this embodiment, the oxide layer 14 is further added.
Are removed by etching so as to cut into the middle of the separation groove.

Finally, the gate insulating film 4 and the gate electrode 5 are formed as shown in FIG. Here, the oxide layer 1
Since the gate insulating film 4 and the gate electrode 5 are etched so as to penetrate into the separation groove,
It is formed so as to wrap around the side surface of the.

According to the present embodiment as described above, the sidewall 11 is formed in the groove 3 forming the element isolation, and the second thermal oxide layer 12 and the third thermal oxide layer 13 are formed by using the sidewall 11 as a mask. Therefore, the element isolation region does not expand beyond the width a of the groove 3 when these thermal oxide layers are formed, and therefore the element formation region 7 can be formed with a good controllability. ..

Further, in this embodiment, since the channel formation region of the transistor is formed so as to extend to a part of the side surface of the groove of the element isolation region, the effective channel width is widened and the narrow channel effect can be suppressed.

Further, since the channel forming region of the transistor is formed so as to be bent, the depletion layer of the transistor is less likely to spread, which also suppresses the narrow channel effect.

Next, another embodiment of the present invention will be described with reference to the drawings. In addition, the description of the conventional technique and the description overlapping with the first embodiment will be appropriately omitted.

FIG. 12 is a sectional view showing an essential part of a method of manufacturing a semiconductor device according to another embodiment of the present invention. Similar to the conventional example and the above-described example, in the figure, 1 is a semiconductor substrate, 2 is a high-concentration impurity layer formed in the substrate 1, 3 is a groove which is a recess formed in the substrate 1, and 4 is a gate insulating film. ,
Reference numeral 5 is a gate electrode, 7 is an element formation region, 11 is a sidewall, 13 is a third thermal oxide layer, and 14 is a fourth oxide layer.

The manufacturing method of this embodiment will be described below with reference to FIG.
(b) will be explained. FIG. 12 (a) shows that in the process of FIG. 7 of the above-described embodiment, the third thermal oxide layer 13 is formed until the element formation region 7 has a shape close to an island, and then the element formation region is further formed. The third thermal oxide layer 13 is formed by thermal oxidation until 7 becomes an island shape completely.

Next, in the same manner as in the above-mentioned embodiment, only the side wall 11 is removed by selective etching, and the fourth oxide layer 14 which fills the groove 3 is formed by the CVD method. Etch back until the surface of the gate appears, and finally, the gate insulating film 4 and the gate electrode 5
Forming a device forming region 7 as shown in FIG.
A semiconductor device having island-shaped element isolations is manufactured.

In this embodiment as well, the second thermal oxide layer 12 and the third thermal oxide layer 13 are formed after the sidewall 11 is formed in the groove 3 for forming the element isolation. , The element isolation region is formed into the groove 3 when the thermal oxide layer is formed.
The element-forming region 7 having an island shape can be formed according to the dimensions with good controllability.

Also in this embodiment, since the channel forming region of the transistor is formed so as to extend to a part of the side surface of the groove of the element isolation region, the effective channel width is widened and the narrow channel effect can be suppressed. ..

Further, since the channel formation region of the transistor is formed so as to be bent, the depletion layer of the transistor is less likely to spread, which also suppresses the narrow channel effect.

[0035]

As described above, according to the present invention, since the semiconductor device has the sidewall formed in the groove for forming the element isolation so that the element isolation region does not spread, it is island-shaped or close to island-shaped. The effect is that the element formation region formed so as to be in a state is finished with good control according to the dimensions.

Further, since the channel forming region of the transistor extends to part of the side surface of the groove of the element isolation region, the effective channel width is widened and the narrow channel effect is suppressed.

Further, since the shape of the channel forming region of the transistor is bent, the depletion layer of the transistor is less likely to spread, which also has the effect of suppressing the narrow channel effect.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view of main steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 12 is a cross-sectional view of each main process showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

[Explanation of symbols]

 1 semiconductor substrate 2 high-concentration impurity layer formed in the substrate 3 groove which is a recess formed in the substrate 4 gate insulating film 5 gate electrode 6 thermal oxide layer 7 element formation region 10 first oxide layer 11 sidewall 12 Second thermal oxide layer 13 Third thermal oxide layer 14 Fourth oxide layer

Claims (2)

[Claims] 1. A step of forming a groove reaching a high-concentration impurity layer formed in a semiconductor substrate in an element isolation region, a step of providing a first oxide layer at the bottom of the groove, and both side walls of the groove. A step of providing a sidewall, a step of forming a second oxide layer on the bottom of the groove by thermal oxidation and removing it, and a step of removing the second oxide layer on the second oxide layer removing portion by thermal oxidation again. A method of manufacturing a semiconductor device, comprising: a step of forming an oxide layer to form an element formation region in an island shape or a shape close to an island shape; and a step of removing the sidewall. 2. A step of forming a groove reaching the high concentration impurity layer formed in the semiconductor substrate in the element isolation region, a step of providing a first oxide layer at the bottom of the groove, and both side walls of the groove. A step of providing a sidewall, a step of forming a second oxide layer on the bottom of the groove by thermal oxidation and removing it, and a step of removing the second oxide layer on the second oxide layer removing portion by thermal oxidation again. A step of forming an oxide layer to form an element formation region in an island shape or a shape close to an island; a step of removing the sidewall; a step of providing a fourth oxide layer up to the middle of the groove; And a step of forming a transistor so as to dig into a part of the side surface of the formation region.