KR100877003B1 - Method for manufacturing non volatile memory device - Google Patents

Abstract

The present invention provides a method of manufacturing a nonvolatile memory device capable of minimizing interference between neighboring cells and preventing a deterioration of cycling characteristics by securing a predetermined distance between a substrate and a control gate in an active region. To this end, the present invention provides a method of forming a floating gate electrically separated by an isolation layer, recessing the isolation layer to partially expose both sidewalls of the floating gate, and spacers on both sidewalls of the exposed floating gate. Forming an oxide, recessing the device isolation layer through the spacer, removing the spacer, and performing an oxidation process to convert the abnormal oxide formed on the floating gate into an oxide layer when the spacer is formed. At the same time as the uniform thickness on the floating gate It provides a method of manufacturing a non-volatile memory device comprising the step of forming an oxide film, and removing the oxide film.

Flash memory device, abnormal oxide, oxidation process, oxide film, pre-clean process

Description

Non-volatile memory device manufacturing method {METHOD FOR MANUFACTURING NON VOLATILE MEMORY DEVICE}

1A to 1C are cross-sectional views illustrating a method of fabricating a flash memory device using a general ASA-STI scheme.

FIG. 2 is a scanning electron microscope (SEM) photograph showing a flash memory device formed by applying a general ASA-STI scheme as shown in FIGS. 1A to 1C.

3A to 3E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to Embodiment 1 of the present invention.

Figure 4 is a TEM (Transmission Electron Microscope) photograph showing the result of the actual cleaning process after the progress.

FIG. 5 is a diagram comparing the EOT of the dielectric film when applying and not applying a wing type spacer technology. FIG.

FIG. 6 is a diagram comparing the BV of the dielectric film when applying the wing type spacer technology and not applying the same; FIG.

7A and 7B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to Embodiment 2 of the present invention;

8 is a TEM photograph showing a nonvolatile memory device formed in accordance with Embodiment 2 of the present invention.

<Explanation of symbols for main parts of the drawings>

30, 70: substrate 31, 71: gate insulating film

32, 72: floating gate 33: pad nitride film

34, 73: wall oxide film 35, 74: device isolation film

36, 36A, 36B, 75: device isolation layer 37: insulating film for spacer

37A: spacer 38: dry etching process

39: wet etching process 41, 79: dielectric film

42, 80: control gate 77: oxidation process

78 oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory device manufacturing technology, and more particularly to a non-volatile memory device, specifically a flash memory device manufacturing method.

Recently, the demand for flash memory devices that can be electrically programmed and erased among nonvolatile memory devices and that does not require a refresh function for rewriting data at regular intervals is increasing. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

In addition, as the integration of devices increases, design rules of such flash memory devices are reduced, resulting in a decrease in program speed and an increase in cell interference. . In particular, the cell interference characteristic is an important factor that determines the characteristics of the device in MLC (Multi Level Cell) rather than SLC (Single Level Cell), and the cell interference characteristic must be improved at the present time when the proportion of MLC is gradually increasing. There is a need to be.

On the other hand, with the reduction of design rules of flash memory devices, a new STI (Shallow Trench Isolation) scheme is proposed for the isolation of various devices. Recently, ASA- is a suitable STI scheme for MLC devices of 60nm or less. Advanced Self Aligned Shallow Trench Isolation (STI) is in the spotlight. The ASA-STI scheme has been applied to forming floating gates of flash memory devices in accordance with a reduction in the overlay margin between the active region and the floating gate. Hereinafter, a general ASA-STI scheme will be described with reference to FIGS. 1A to 1C.

First, as shown in FIG. 1A, the tunnel oxide film 11, the floating gate 12, and the pad nitride film 13 are sequentially formed on the semiconductor substrate 10.

Subsequently, the pad nitride layer 13, the floating gate 12, the tunnel oxide layer 11, and the substrate 10 are etched to form trenches having a predetermined depth.

Subsequently, after the wall oxide film 14 is formed along the inner surface of the trench, the HDP film 15 deposited by the high density plasma (CVD) chemical vapor deposition (CVD) method is deposited to fill the trench.

Subsequently, a chemical mechanical polishing (hereinafter referred to as CMP) process is performed. As a result, the device isolation layer 16 embedded in the trench is formed.

Subsequently, as shown in FIG. 1B, the pad nitride film 13 is removed. In this case, the device isolation layer 16 may also have a predetermined thickness removed.

Subsequently, the device isolation layer 16A of the cell region is recessed to a predetermined depth using a Periphery Closed Layer (PCL) mask (not shown), wherein the peripheral circuit region is closed and the cell region has an open structure. . At this time, the effective height of the recessed device isolation layer 16A becomes 'EFH'. In general, EFH is an abbreviation of “Effective Field oxide Height” and refers to the height of the device isolation layer 16A that protrudes above the substrate 10 of the active region.

Thereafter, a stripping process is performed to remove the PCL mask.

Subsequently, as shown in FIG. 1C, the dielectric film 17 is formed along the entire top surface step formed by the recessed device isolation film 16A. Then, the control gate 18 is formed on the dielectric film 17.

FIG. 2 is a scanning electron microscope (SEM) photograph of a flash memory device formed by applying a general ASA-STI scheme as shown in FIGS. 1A to 1C.

Hereinafter, the problem of the ASA-STI scheme will be described with reference to FIG. 2. Referring to FIG. 2, when the ASA-STI scheme is applied, control of the EFH of the device isolation layer is not easy, so that the region where the EFH is adjusted is increased due to the increase in capacitance. There is an increasing problem. Therefore, if the EFH of the device isolation layer is reduced to improve such interference characteristics, the separation distance D1 between the substrate 10 and the control gate 18 in the active region is further reduced, thereby reducing the substrate 10 and the control gate 18. The leakage current of the device causes a problem that the cycling characteristics of the device (repeated program and erase operation characteristics) are deteriorated.

Accordingly, the present invention has been made to solve the above problems of the prior art, has the following objects.

First, an object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of minimizing interference between neighboring cells.

Second, another object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of preventing a deterioration in cycling characteristics by securing a predetermined distance between a substrate and a control gate in an active region.

According to an aspect of the present invention, there is provided a method of forming a floating gate electrically separated by a device isolation film, recessing the device isolation film to partially expose both sidewalls of the floating gate; Forming spacers on both sidewalls of the exposed floating gate, recessing the device isolation layer through the spacers, removing the spacers, and performing an oxidation process to form the spacers on the floating gates. A method of manufacturing a nonvolatile memory device includes converting an abnormal oxide formed in an oxide film into an oxide film, and simultaneously forming an oxide film having a uniform thickness on the floating gate, and removing the oxide film.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same components.

Example 1

3A to 3E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to Embodiment 1 of the present invention.

First, as shown in FIG. 3A, a gate insulating film 31, a conductive film 32 for a gate electrode (floating gate), and a pad nitride film 33 are sequentially formed on the semiconductor substrate 30. Here, the gate insulating layer 31 functions as a tunnel oxide layer of a general flash memory device and may be formed of an oxide layer material including an oxide layer or a nitride layer. In addition, the conductive film 32 may be formed of doped or undoped polysilicon.

In this case, a buffer oxide layer (not shown) may be further formed between the floating gate 32 and the pad nitride layer 33 to reduce the stress applied to the conductive layer 32 when the pad nitride layer 33 is formed. .

Subsequently, the pad nitride film 33, the conductive film 32, the gate insulating film 31, and the substrate 30 are etched to form trenches (not shown) having a predetermined depth. Here, the conductive layers 32 separated from each other by the trench function as floating gates electrically separated from each other, and thus, '32' will be referred to as a 'floating gate'.

Subsequently, wall oxidation is performed to compensate for damage to the trench inner and bottom surfaces during the STI etching process, to round the upper corners, and to reduce the critical dimension (CD) of the active region. Perform the process. As a result, a wall oxide layer 34 is formed along the inner surface of the trench.

Subsequently, an insulating layer 35 for device isolation is deposited to fill the trench. In this case, it is preferable to form the isolation film 35 for element isolation as an HDP film having excellent embedding characteristics so that voids do not occur in the trench. Thereafter, the CMP process is performed to form the device isolation layer 36 embedded in the trench.

Subsequently, as illustrated in FIG. 3B, the pad nitride layer 33 is removed by performing a wet etching process. In this case, the device isolation layer 36 may also have a predetermined thickness removed.

Subsequently, the device isolation layer 36A in the cell region is recessed by a predetermined depth using a PCL mask (not shown). At this time, the effective height of the recessed device isolation layer 36A becomes 'EFH'.

Subsequently, a spacer insulating film 37 having a predetermined thickness is deposited on the floating gate 32 including the recessed device isolation film 36A. In this case, the spacer insulating layer 37 is formed of a material having an etching selectivity with respect to the device isolation layer 36A. For example, the spacer insulating layer 37 is formed of a nitride film-based material to have an etching rate different from that of the material forming the device isolation layer 36A.

Subsequently, as shown in FIG. 3C, a dry etching process 38 is performed to etch the spacer insulating film 37 (see FIG. 3B). As a result, spacers 37A are formed on both sidewalls of the conductive film 32 exposed on the device isolation film 36A.

Next, as shown in FIG. 3D, a wet etching process 39 using the spacer 37A as a mask is performed. In the wet etching process 39, a buffered oxide etchant (hereinafter referred to as BOE) or hydrofluoric acid (HF) is used. In this case, BOE refers to a solution in which HF and NH ₄ F are mixed at 100: 1 or 300: 1. As a result, the device isolation film 36B is recessed again to a predetermined width and depth. At this time, the etching in the lateral direction is faster than the etching in the depth direction due to the etching characteristics of the wet etching process 39.

Subsequently, as shown in FIG. 3E, the wet etching process is performed to remove the spacer 37A, and then a pre-clean process is performed. In the pre-cleaning process, BOE or HF is used.

When the spacer 37A is removed according to the exemplary embodiment of the present invention, there is no plasma attack applied to the substrate 30 and the EFH may be uniformly maintained at both sides of the floating gate 32. Therefore, interference between neighboring cells can be suppressed.

In addition, since the device isolation layer 36B having a predetermined thickness remains on both sides of the floating gate 32, the gap between the substrate 30 in the active region and the control gate 42 to be formed through a subsequent process may be kept constant. . Therefore, deterioration of the cycling characteristics of an element can be prevented.

Subsequently, the dielectric film 41 is formed along the level difference of the upper surface of the floating gate 32 including the device isolation film 36B, and the control gate 42 is formed on the dielectric film 41. At this time, the dielectric film 41 is preferably formed of an oxide / nitride / oxide film (Oxide / Nitride / Oxide, ONO) structure.

As described above, according to the exemplary embodiment of the present invention, as the insulating film for separating the adjacent floating gates 32 from each other, not only the device isolation film 36B but also the dielectric film 41 made of a material different from the device isolation film 36B is provided. As such, interference between neighboring cells can be minimized.

Example 2

7A and 7B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to Embodiment 2 of the present invention. Here, for the convenience of description, the same process steps as those of Embodiment 1 of the present invention will be omitted, and only process steps that will be performed to solve problems that may occur in Embodiment 1 of the present invention will be described.

For example, when manufacturing a flash memory device according to the first embodiment of the present invention, due to plasma damage and contamination during the dry etching process 38 for forming the spacer 37A as shown in Figure 3c There is a concern that abnormal oxides of non-uniform thickness may be formed on the upper surface of the floating gate 32.

In particular, such an abnormal oxide is not only an incomplete oxide film material but also has a problem that the thickness thereof is non-uniform, and thus remains unremoved even during a subsequent pre-clean process. This is as shown in FIG.

FIG. 4 is a TEM (Transmission Electron Microscope) photograph showing a result drawing after actually performing a pre-cleaning process. Referring to FIG. 4, it can be seen that even after the pre-cleaning process, the abnormal oxide (AO) is not removed but remains on the floating gate 32 as it is. Here, 'CR' is a capping layer for TEM analysis and is not applied in an actual process.

As described above, the abnormal oxide AO remaining on the floating gate 32 causes various problems as follows. For example, the equivalent oxide thickness (hereinafter referred to as EOT) on the floating gate 32 is not only nonuniform, but also increases the EOT on the floating gate 32 as a whole. This is as shown in FIG.

FIG. 5 is a diagram comparing the EOT of a dielectric film when applying a wing type spacer technology and not applying it. FIG.

Referring to FIG. 5, it can be seen that the EOT of the dielectric film ONO is increased when manufacturing a flash memory device to which the spacer forming technology is applied, than when manufacturing a flash memory device to which the spacer forming technology is not applied. That is, when the spacer technology is applied as described above, the EOT on the floating gate 32 is increased by the abnormal oxide AO generated as in FIG. 4. This increase in EOT is problematic because the coupling ratio of the flash memory device is degraded.

In addition, the abnormal oxide AO degrades the interface property between the floating gate 32 and the dielectric film 41, resulting in a breakdown voltage breakdown voltage (BV) of the dielectric film. This is as shown in FIG.

FIG. 6 is a diagram comparing BV of a dielectric film when applying a wing type spacer technology and not applying it. FIG.

Referring to FIG. 6, it can be seen that the BV of the dielectric film is lowered when manufacturing the flash memory device using the spacer technology than when manufacturing the flash memory device without the spacer forming technology. That is, when the spacer technology is applied as described above, the BV of the dielectric film ONO is lowered by the abnormal oxide AO generated as in FIG. 4.

As a result, in order to solve this problem, it is necessary to remove the abnormal oxide. Therefore, in Example 2 of the present invention, the following process is carried out.

First, as shown in FIG. 7A, the oxidation process 77 is performed in the same manner as in FIG. 3D according to Embodiment 1 of the present invention. As a result, an oxide film 78 having a uniform thickness is formed on the floating gate 72.

In particular, during the oxidation process 77, the abnormal oxide (not shown) existing on the floating gate 72 is converted into an oxide film 78 while being converted into a complete oxide film material. Therefore, it can be easily removed during the subsequent pre-cleaning process. The process conditions of the oxidation process 77 will be described in detail with reference to Table 1 below.

In Table 1, the 'LOAD' process is a process step for pulling a boat (BOAT) on which wafers are mounted into a high temperature furnace, and moving the boat at a speed of 100 to 150 mm / min. desirable. It is also preferable to proceed at a temperature of about 650 ° C.

The subsequent 'RECOVERY' process waits at the same temperature as the 'LOAD' process in order to keep the temperature of each wafer constant, and the 'RAMP-UP' process is heated to raise the required process temperature. Heating at a temperature gradient of 5 ° C./min is preferred.

In addition, the 'STAB' process is a process step for all wafers to maintain the same temperature and to prevent overshoot that may occur when the temperature rises, and the 'O2 Purge' and 'Burn-1' processes are furnaces. into the by induction to enable the right and the O ₂ reaction, the process steps to prevent an accident such as the explosion time before the H ₂ gas is introduced to create the atmosphere of the furnace in O ₂ atmosphere is the H ₂ gas inlet.

In addition, the 'Burn-2' process is a process step of converting the furnace into a wet (Wet) atmosphere by reacting a small amount of O ₂ and H ₂ gas.

In particular, the 'Wet OX' process is a main oxidation process step that proceeds to obtain the required oxide film thickness, the process conditions during the main oxidation process is the most important factor that determines the nature and thickness of the oxide film (78). To this end, in the 'Wet OX' process according to Example 2 of the present invention, it is important to set the flow rate ratio of the gas used to be O ₂ : H ₂ = 1: 1.5.

That is, in the 'Burn-1' and 'Burn-2' processes, the flow rate ratio of the used gas is maintained at the ratio of O ₂ : H ₂ = 1: 1 as before, but in the 'Wet OX' process, O ₂ : The oxidation rate is increased by increasing the ratio of H ₂ = 1: 1.5. Through this, the oxide film 78 may be grown to a uniform thickness as desired. For example, in the 'Burn-1' process, O ₂ : H ₂ = 3: 3 slm (standard liter per minute) is used as an optimal condition, but their flow rates can be controlled within ± 10%, respectively. In the 'Wet OX' process, O ₂ : H ₂ = 6.67: 10 slm is used under optimum conditions, but their flow rates can be controlled within ± 10% of each.

In addition, in the 'Wet OX' process, the flow rate of the O ₂ and H ₂ gases used may be increased than in the normal main oxidation process to enable the growth of the oxide film 78 having a uniform thickness.

Meanwhile, the thickness of the oxide film 78 may be affected by the process temperature of the 'Wet OX' process and the overall process time of the oxidation process 77. Here, the 'Wet OX' process is preferably carried out in a temperature range of 700 ~ 750 ℃. For example, the oxidation process 77 is performed for about 12 minutes for 50-nm uniform oxide film growth.

For reference, in the normal oxidation process, the ratio of O ₂ : H ₂ = 1: 1 was maintained in consideration of the reactivity of O ₂ and H ₂ in the 'Wet OX' process, and the flow rates of O ₂ and H ₂ gases used at this time Were set to 8 L each. However, according to the conditions of the oxidation process, in the presence of contaminants or the above-mentioned oxide, the oxidation is partially interrupted at the portion where the oxide is present. there is a problem.

Therefore, in Example 2 of the present invention, the oxidation rate is increased by increasing the ratio of O ₂ : H ₂ = 1: 1.5 in the 'Wet OX' process, which is the main oxidation process, and the flow rates of O ₂ and H ₂ gas are at least 8 L or more, respectively. To increase.

In addition, the 'O2-Anneal' process is a process step for completely burning excess H ₂ gas remaining after the 'Wet OX' process, and the 'N2-Anneal' process is the O remaining after the 'Wet OX' process. Process step to remove ₂ and give an annealing effect.

In addition, the 'RAMPDOWN' process is a process step of lowering the temperature required to pull out the wafers, and the 'UNLOAD' process is a process step of taking out the wafer that has been placed in the furnace out of the furnace. Here, the 'UNLOAD' process is preferably performed at a temperature of about 650 ℃.

Subsequently, as shown in FIG. 7B, a pre-cleaning process is performed to remove all of the oxide film 78 present on the floating gate 72. As a result, the abnormal oxide no longer exists on the floating gate 72. Here, it is preferable to use BOE or HF at the time of a pre-cleaning process.

Subsequently, after the dielectric film 79 is formed along the top surface of the device isolation film 75 including the floating gate 72, the control gate 80 is formed on the dielectric film 79. Here, the dielectric film 79 is preferably formed in an ONO structure.

8 is a TEM photograph showing a flash memory device formed according to Embodiment 2 of the present invention. Referring to FIG. 8, it can be seen that the abnormal oxide AO as shown in FIG. 4 is completely removed after the pre-cleaning process.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects are obtained.

First, according to the present invention, spacers are formed on both walls of the floating gate electrically separated from each other by the device isolation film, and the device isolation film is recessed through the spacers, thereby suppressing the change in the effective height of the device isolation film on both sides of the floating gate. Interference can be minimized. In addition, by allowing the isolation film and the dielectric film, which is a heterogeneous film, to exist in the recessed device isolation film, interference between neighboring cells can be further reduced.

Second, according to the present invention, the device isolation film is recessed through spacers formed on both sidewalls of the floating gate, so that the device isolation film having a predetermined thickness remains on both sides of the floating gate even after the device isolation film recesses. Can be kept constant to some extent, thereby improving the cycling characteristics of the device.

Third, according to the present invention, by converting the abnormal oxide which may be generated on the floating gate when forming the spacer through a separate oxidation process into an oxide film having a uniform thickness, the abnormal oxide during the subsequent pre-clean process This can be easily removed. Through this, the electrical thickness of the dielectric film on the floating gate can be reduced and the breakdown voltage characteristic of the dielectric film can be improved.

Claims (10)

Forming a floating gate electrically separated by an isolation layer; Recessing the device isolation layer to partially expose both sidewalls of the floating gate; Forming spacers on both sidewalls of the exposed floating gate; Recessing the device isolation layer through the spacer; Removing the spacers; Performing an oxidation process to convert an abnormal oxide formed on the floating gate into an oxide film at the time of forming the spacer and to form an oxide film having a uniform thickness on the floating gate; And Removing the oxide film Nonvolatile memory device manufacturing method comprising a. The method of claim 1, After removing the oxide film, Forming a dielectric film along a step top surface of the resultant product from which the oxide film is removed; And Forming a control gate on the dielectric layer Non-volatile memory device manufacturing method further comprising. The method of claim 2, Removing the oxide film, A nonvolatile memory device manufacturing method comprising performing a pre-cleaning step that proceeds before forming the dielectric film. The method according to any one of claims 1 to 3, The oxidation process is a non-volatile memory device manufacturing method using the O ₂ and H ₂ gas. The method of claim 4, wherein The oxidation process includes a burn process and a main oxidation process. The method of claim 5, wherein In the burn process, the flow rate ratio (O ₂ : H ₂ ) of the O ₂ and H ₂ gases is 1: 1. The method of claim 6, The burn process is a non-volatile memory device manufacturing method for adjusting the flow rate of the O ₂ and H ₂ gas equally to 3 ± 10% slm. The method of claim 5, wherein The main oxidation process is a non-volatile memory device manufacturing method of the flow ratio of the O ₂ and H ₂ gas (O ₂ : H ₂ ) 1: 1.5. The method of claim 8, The main oxidation process is a non-volatile memory device manufacturing method for adjusting the flow rate of the O ₂ and H ₂ gas to O ₂ = 6.67 ± 10% slm, H ₂ = 10 ± 10% slm, respectively. The method of claim 5, wherein The burn process and the main oxidation process is performed in a temperature range of 700 ~ 750 ℃ nonvolatile memory device manufacturing method.

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