JP2003324146A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device which can restrain stress applied to a semiconductor substrate in the upper part of a trench groove sidewall without forming a recess in the end of a trench embedding insulation film in forming a trench groove separation region separating an active region. <P>SOLUTION: A sidewall film 6 of a boron and phosphorus-containing silicon oxide film is formed in the sidewall of a lamination film of a silicon oxide film 2 and a silicon nitride film 3 on the active region of a silicon substrate 1. The silicon substrate 1 is subjected to wet etching and tapered by using the sidewall film 6 and the silicon nitride film 3 as a mask, and successively, it is subjected to anisotropic etching and a trench groove 8 is formed. After the sidewall film 6 is removed, a thermal oxide film is formed inside the trench groove 8, and the trench groove 8 is completely filled with the silicon oxide film. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an active region on a semiconductor substrate is separated by a trench groove and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, trench isolation has been used for element isolation in an active region of a semiconductor integrated circuit device. Hereinafter, a conventional method of manufacturing a semiconductor device in which an active region is separated by a trench groove and a silicon substrate above a sidewall of the trench groove has a forward tapered shape will be described with reference to the drawings. 15 to 23 show a conventional manufacturing method.

First, a silicon oxide film 12 is formed on a silicon substrate 11, and then a silicon nitride film 13 is deposited (FIG. 15). Next, a photoresist pattern 14 is formed so that the isolation region is opened (FIG. 16). Using the photoresist pattern 14 as a mask, the silicon nitride film 13 and the silicon oxide film 12 in the isolation region are etched to expose the silicon substrate 11 (FIG. 17). Exposed silicon substrate 1 using silicon nitride film 13 remaining on the active region after removing resist pattern 14 as a mask
At the same time that 1 is etched by isotropic etching, the silicon substrate below the end of the silicon nitride film 13 is also etched laterally (FIG. 18). Thereby, the silicon substrate 11
It is possible to form a shallow trench groove having a forward tapered corner shape 15.

Next, the silicon nitride film 1 remaining on the active region
The deep trench groove 16 is formed by anisotropically etching the silicon substrate 11 using 3 as a mask. As a result, it is possible to obtain a shape having a forward taper angle on the silicon substrate above the side wall of the trench groove 16. After forming the trench groove 16, a thermal oxidation process is performed to form a silicon oxide film 17 on the inner wall thereof (FIG. 19). After that, C is formed inside the trench groove 16 and above the silicon nitride film 13.
The oxide film 18 is deposited by the VD method so that the trench groove 16 is completely filled (FIG. 20). At this time, since the forward tapered angle-shaped portion formed on the silicon substrate 11 below the end portion of the silicon nitride film 13 has a shape in which the silicon nitride film 13 is protruded, the oxide film 18 is not sufficiently embedded and the cavity is not formed. 19 is formed.

Oxide film 18 deposited by the CVD method
Are polished and planarized by CMP (FIG. 21). At this time, the silicon nitride film 13 functions as a stopper film during polishing by CMP. After the planarization by CMP is finished, the silicon nitride film 13 on the active region is removed by hot phosphoric acid (FIG. 22), the silicon oxide film 12 is removed by hydrofluoric acid solution, and the active region separated by the trench groove 16 is removed. Are formed (FIG. 23).

As described above, by forming the forward taper angle shape 15 on the silicon substrate 11 above the sidewall of the trench groove, the stress applied to the silicon substrate at the boundary surface between the silicon substrate 11 and the buried oxide film 18 of the trench groove 16 is reduced. Since it can be relaxed, the film thickness uniformity of, for example, the gate oxide film formed on the silicon substrate 11 at the end of the active region at the time of forming the gate oxide film can be improved.

[0007]

However, in the above-described conventional method for manufacturing a semiconductor device, the silicon nitride film 13 is projected on the shape 15 of the silicon substrate 11 having the forward taper angle. Therefore, the thermal oxide film 1 on the inner wall
In the step of depositing the buried oxide film 18 in the trench groove 16 in which the trenches 7 are formed by CVD, the trench buried oxide film is not sufficiently deposited in the portion 15 having the forward taper angle, and a cavity 19 is formed. Therefore, after the CMP planarization after depositing the trench filling oxide film 18, the removal of the silicon nitride film 13 in the active region and the removal of the silicon oxide film 12 in the active region, a concave recess is formed at the boundary between the activation region and the trench filling oxide film 18. You can do 20.

Active region and trench buried oxide film 18
When the gate electrode is formed in the state where the recessed dent 20 exists at the boundary of, the gate material is likely to remain along the recessed dent 20, resulting in leakage between the gate electrodes. In addition, when a voltage is applied to the gate electrode, there arises a problem that an electric field is concentrated on the gate electrode in the recess 20.

The present invention solves the above-mentioned conventional problems, and does not generate a concave depression at the boundary between the active region and the trench-filled insulating film, and the semiconductor substrate on the upper side wall of the trench groove ( An object of the present invention is to provide a semiconductor device capable of suppressing stress applied to the active region end portion) and a method for manufacturing the same.

[0010]

In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device in which a trench groove for separating an active region is formed in a semiconductor substrate and an insulating film is embedded in the trench groove. The semiconductor substrate on the upper side wall of the trench groove has a shape having a forward taper angle, the inclined surface is provided on the upper side wall of the trench groove, and the insulating film is also embedded on the inclined surface of the trench groove. To do.

According to the semiconductor device of the present invention, since the semiconductor substrate on the side wall of the trench groove has a forward taper angle shape, the stress applied to the semiconductor substrate at the end of the active region can be relieved. For example, when forming a MOS transistor, the film thickness of the gate oxide film, which depends on stress, can be uniformly improved at the end of the active region when the gate oxide film is formed. In addition, since the insulating film filling the trench groove is also buried on the inclined surface formed on the upper portion of the sidewall of the trench groove, the conventional concave type is formed at the boundary between the active region and the insulating film buried in the trench groove. When forming a MOS transistor as described above, there is no recess, and it is possible to suppress the remaining gate electrode material when forming the gate electrode and the electric field concentration when a voltage is applied to the gate electrode.

A method of manufacturing a semiconductor device according to the present invention comprises a step of depositing a first insulating film on a semiconductor substrate and a step of selectively removing the first insulating film so that an isolation region of the semiconductor substrate is opened. A step of forming a second insulating film on the side wall of the opened first insulating film, isotropic etching of the semiconductor substrate using the first and second insulating films as a mask, and then anisotropic etching By doing so, the method includes the step of forming the trench groove and the step of filling at least the inside of the trench groove with the third insulating film after removing the second insulating film.

According to this method for manufacturing a semiconductor device of the present invention, the semiconductor substrate on the upper side wall of the trench groove can be made to have a forward taper angle shape by isotropic etching of the semiconductor substrate. When the gate oxide film is formed, the film thickness of the gate oxide film depending on the stress can be made uniform at the end of the active region when the gate oxide film is formed. Can be improved. In addition, since the trench groove is filled with the insulating film after the second insulating film that has been subjected to the isotropic etching of the semiconductor substrate is removed, the forward taper square portion of the semiconductor substrate (on the inclined surface of the upper portion of the trench sidewall).
In addition, the insulating film can be completely embedded, and the conventional concave depression is not formed at the boundary between the active region and the embedded insulating film. When forming a MOS transistor as described above, when forming a gate electrode, It is possible to suppress the rest of the gate electrode material and the electric field concentration when a voltage is applied to the gate electrode.

The first insulating film is composed of two lower and upper insulating films, the lower insulating film is a silicon oxide film, the upper insulating film is a silicon nitride film, and the second insulating film is boron.
A silicon oxide film containing impurities such as phosphorus can be used.

When the semiconductor substrate is isotropically etched in the step of forming the trench groove, it is desirable that the lateral etching amount of the isotropic etching be equal to or less than the film thickness of the second insulating film.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. 1 to 14 are sectional views showing the steps of manufacturing a semiconductor device according to the present invention. A silicon oxide film 2 having a thickness of 15 nm is formed on a silicon substrate 1, and subsequently a silicon nitride film 3 having a thickness of 100 to 200 nm is formed.
Are deposited (FIG. 1). Next, a photoresist pattern 4 is formed so as to open the isolation region (FIG. 2), and the silicon nitride film 3 and the silicon oxide film 2 in the isolation region are etched by using the photoresist pattern 4 as a mask. The substrate 1 is exposed (FIG. 3).

After removing the photoresist pattern 4 (FIG. 4), a silicon oxide film 5 containing boron and phosphorus of 20 to 200 nm is deposited on the silicon nitride film 3 on the active region and on the silicon substrate 1 to be the isolation region. (Fig. 5).
Next, the wafer on which the silicon oxide film 5 containing boron and phosphorus is deposited is entirely etched by anisotropic dry etching, and boron is formed on the side wall of the laminated film of the silicon oxide film 2 and the silicon nitride film 3 on the active region. Then, the sidewall film 6 of the silicon oxide film 5 containing phosphorus is formed (FIG. 6).

Using the sidewall film 6 of the silicon oxide film 5 containing boron and phosphorus and the silicon nitride film 3 as a mask, the silicon substrate 1 in the isolation region is isotropically etched by wet etching for 20 to 200 nm to form a shallow trench groove. Form (FIG. 7). At this time, since the etching also proceeds in the lateral direction, the silicon substrate 1 under the sidewall film 6 is also etched, and this portion has a forward tapered corner shape 7. Further, the wet etching amount is set to be equal to or less than the thickness of the sidewall film 6 so that the lateral etching during the wet etching does not reach the silicon substrate 1 in the activation region.

Further, with the side wall film 6 of the silicon oxide film 5 containing boron and phosphorus and the silicon nitride film 3 as a mask again, the silicon substrate 1 is 300 to 500 nm thick.
Anisotropic etching is performed to form a deep trench groove 8 (FIG. 8). Then, a silicon oxide film 5 containing boron and phosphorus
After the sidewall film 6 is selectively removed with a hydrofluoric acid-based wet etching solution (FIG. 9), a thermal oxide film 9 is formed inside the trench groove 8 (FIG. 10), and then the trench groove 8 is completely removed. A silicon oxide film 10 to the extent of being buried is deposited on the entire surface of the wafer (FIG. 11). The wafer having the silicon oxide film 10 deposited on the entire surface is planarized by CMP polishing (FIG. 12), the silicon nitride film 3 remaining on the active region is removed by hot phosphoric acid (FIG. 13), and the lower silicon oxide film 2 is removed. Are removed with a hydrofluoric acid solution to trench-separate the activated region (see FIG. 1).
4).

As described above, according to the present embodiment, since the silicon substrate 1 on the upper side wall of the trench groove 8 has a forward taper angle shape, the stress applied to the silicon substrate 1 at the end of the active region is relaxed. be able to. As a result, when a MOS transistor is formed thereafter, when the gate oxide film is formed, the thickness of the gate oxide film at the end of the active region is
Non-uniformity due to stress can be improved. Further, in the process of FIG. 7, the silicon substrate 1 using the sidewall film 6 as a mask is isotropically etched to form the silicon substrate 1 in a forward taper angle shape, and then the sidewall film 6 is removed in the process of FIG. Oxide film 10
Since it is buried in, it is possible to prevent a concave recess from being generated at the boundary between the active region and the trench groove filling oxide film. Therefore, the gate electrode material does not remain along the edge recess of the trench groove during dry etching for forming the gate electrode of the MOS transistor, unlike the conventional case.
Further, electric field concentration can be suppressed when a voltage is applied to the formed gate electrode.

In the above embodiment, the sidewall film 6 formed on the side wall of the laminated film of the silicon oxide film 2 and the silicon nitride film 3 is the silicon oxide film containing boron and phosphorus. Any film may be used as long as the film has a faster wet etching rate than the silicon oxide film 2 and the silicon nitride film 3 formed in 1. By using a film having a high wet etching rate, the sidewall removal process can be performed with almost no side etching of the silicon oxide film 2.

[0022]

As described above, according to the present invention, since the semiconductor substrate above the side wall of the trench groove has a forward taper angle shape, the stress applied to the semiconductor substrate at the end of the active region can be relaxed. As a result, when forming a MOS transistor, it is possible to improve the film thickness uniformity of the gate oxide film at the end of the active region when forming the gate oxide film.
Furthermore, since a concave depression is not generated at the boundary between the active region and the trench groove filling insulating film, when forming a MOS transistor, the gate electrode material does not remain along the trench groove during the dry etching for forming the gate electrode,
Further, electric field concentration can be suppressed when a voltage is applied to the formed gate electrode.

[Brief description of drawings]

FIG. 1 is a sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 12 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 13 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 14 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device of the present invention.

FIG. 15 is a cross-sectional view showing a step in a conventional semiconductor device manufacturing method.

FIG. 16 is a cross-sectional view showing one step in a conventional method for manufacturing a semiconductor device.

FIG. 17 is a cross-sectional view showing a step of a conventional method for manufacturing a semiconductor device.

FIG. 18 is a cross-sectional view showing a step in a conventional method for manufacturing a semiconductor device.

FIG. 19 is a cross-sectional view showing a step in a conventional semiconductor device manufacturing method.

FIG. 20 is a cross-sectional view showing a step of a conventional method for manufacturing a semiconductor device.

FIG. 21 is a cross-sectional view showing a step of a conventional method for manufacturing a semiconductor device.

FIG. 22 is a cross-sectional view showing a step of a conventional method for manufacturing a semiconductor device.

FIG. 23 is a cross-sectional view showing a step in a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 Silicon substrate 2 Silicon oxide film 3 Silicon nitride film 4 Photoresist pattern 5 Silicon oxide film containing boron and phosphorus 6 Sidewall film 7 Tapered portion 8 trench grooves 9 Thermal oxide film 10 Trench buried oxide film 11 Silicon substrate 12 Silicon oxide film 13 Silicon nitride film 14 Photoresist pattern 15 Tapered portion 16 trench groove 17 Thermal oxide film 18 Trench buried oxide film 19 cavity 20 concave depression

Claims (4)

[Claims] 1. A semiconductor device in which a trench groove for separating an active region is formed in a semiconductor substrate, and an insulating film is embedded in the trench groove, wherein the semiconductor substrate above a sidewall of the trench groove has a forward taper angle. A semiconductor device having the shape described above, wherein an inclined surface is provided on an upper portion of a side wall of the trench groove, and the insulating film is embedded also on the inclined surface of the trench groove. 2. A step of depositing a first insulating film on a semiconductor substrate, a step of selectively removing the first insulating film so that an isolation region of the semiconductor substrate is opened, and the opening. Forming a second insulating film on the side wall of the first insulating film, and isotropically etching the semiconductor substrate using the first and second insulating films as a mask, and then anisotropically etching the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 1, further comprising: a step of forming a trench groove, and a step of removing at least the second insulating film and filling at least the inside of the trench groove with a third insulating film. 3. The first insulating film is composed of two layers of insulating films, a lower layer and an upper layer, the lower insulating film is a silicon oxide film, and the upper insulating film is a silicon nitride film. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the second insulating film is a silicon oxide film containing impurities. 4. When the semiconductor substrate is isotropically etched in the step of forming the trench groove, a lateral etching amount of the isotropic etching is set to be equal to or less than a film thickness of the second insulating film. 4. The method of manufacturing a semiconductor device according to claim 2, wherein