KR101002550B1 - Method of manufacturing a flash memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory device, which increases the coupling ratio by increasing the height of the floating gate protruding out of the device isolation layer, and subsequently forms a control gate formed by etching a portion of the device isolation layer between the floating gates. Is formed at a position between the floating gates to reduce the interference effect, and when etching a portion of the device isolation layer, dry etching is performed using a spacer to etch the device isolation layer to a desired height, and then through wet etching. Disclosed is a method of manufacturing a flash memory device capable of protecting a device isolation film formed on a sidewall of a floating gate by removing a spacer.

Flash, Floating Gate, Coupling Ratio, Interference, Sidewall

Description

Method of manufacturing a flash memory device

1 is a cross-sectional view of a device for explaining a method of manufacturing a flash memory device according to the prior art.

2 is a graph illustrating a relationship between an interference ratio and a coupling ratio according to a height of a floating gate and a distance between floating gates of a flash memory device.

3 to 7 are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10, 100: semiconductor substrate 11, 101: tunnel oxide film

12, 102: conductive film for floating gate 13, 103: trench

14, 104: device isolation film 18, 109: dielectric film

105: sidewall 15, 106: the first oxide film

16, 107: nitride film 17, 108: second oxide film

110: conductive film for the control gate

The present invention relates to a flash memory device, and more particularly to a method of manufacturing a flash memory device for reducing the interference effect between the floating gates.

In a NAND type flash memory device, a plurality of cells for storing data are connected in series to form a string, and a drain select transistor and a source select transistor are formed between the cell string and the drain and the cell string and the source, respectively. A cell of such a NAND flash memory device is formed by forming a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on a semiconductor substrate, and forming junctions on both sides of the gate.

In such a NAND flash memory device, it is very important to keep the cell state constant because the state of the cell is affected by the operation of adjacent neighboring cells. The change of the state of the cell due to the operation of adjacent neighboring cells, in particular the program operation, is called an interference effect. That is, the interference effect means that when the second cell adjacent to the first cell to be read is programmed, the threshold voltage of the first cell is higher than the threshold voltage of the first cell when the first cell is read due to the capacitance action caused by the charge change of the floating gate of the second cell. This refers to a phenomenon in which the threshold voltage is read, and refers to a phenomenon in which the state of the actual cell is distorted by the change of the state of the adjacent cell, although the charge of the floating gate of the read cell does not change. This interference effect causes the state of the cell to change, which results in an increase in the defective rate resulting in a lower yield. Therefore, minimizing the interference effect can be said to be effective to keep the state of the cell constant.

Meanwhile, a part of the device isolation layer and the floating gate are formed by using a self-aligned shallow trench isolation (SA-STI) process in a manufacturing process of a general NAND flash memory device. Referring to FIG. Same as

After the tunnel oxide film 11 and the first polysilicon film 12 are formed on the semiconductor substrate 10, predetermined regions of the first polysilicon film 12 and the tunnel oxide film 11 are etched to form a semiconductor substrate 10. ) To form a trench 13 by etching to a predetermined depth, the insulating film is buried and a polishing process is performed to form the device isolation film 14. Thereafter, the first oxide film 15, the nitride film 16, and the second oxide film 17 are sequentially formed to form the dielectric film 18.

When the flash memory device is manufactured using the SA-STI process as described above, since the device isolation layer is formed between the first polysilicon layer and the first polysilicon layer adjacent to the floating polysilicon layer, the first polysilicon layer is formed between the first polysilicon layers. Interference may occur in the.

2 is a graph showing the interference effect and the coupling ratio according to the height and distance between the floating gates.

Referring to FIG. 2, the gate-to-gate interface is proportional to the distance between the floating gates and the height of the floating gates. That is, if the distance between the floating gates is far and the height of the floating gate decreases, the interference decreases. On the contrary, when the height of the floating gate is decreased, the interface area between the floating gate and the control gate is decreased, thereby reducing the coupling ratio.

The technical problem to be achieved by the present invention is to increase the coupling ratio by increasing the height of the floating gate protruding to the outside of the device isolation layer, the control gate formed by etching a portion of the device isolation layer between the floating gate, the position between the floating gate In order to reduce the interference effect and to dry a portion of the device isolation layer, dry etching is performed by using a spacer to etch the device isolation layer to a desired height, and then the spacer is removed by wet etching. The present invention provides a method of manufacturing a flash memory device capable of protecting a device isolation layer formed on a sidewall of a floating gate.

In the method of manufacturing a flash memory device according to an embodiment of the present invention, after forming a tunnel oxide film and a floating gate conductive film on a semiconductor substrate, the trench is formed by etching the conductive film for the floating gate, the tunnel oxide film, and a portion of the semiconductor substrate. Forming a device isolation layer by filling an insulating film in the trench, and etching an upper end of the device isolation layer to control EFH of the device isolation layer, and forming a sidewall on a sidewall of the conductive gate layer for the floating gate. And etching the upper end of the device isolation layer to an area under the tunnel oxide layer, removing the sidewall, and forming a conductive layer for the dielectric layer and the control gate on the entire structure. The etching rate is faster than that of the device isolation layer.

The sidewalls have a wet etching rate of 2 to 10 times that of the device isolation layer. Each of the floating gate conductive film and the control gate conductive film is formed of a polysilicon film, and the floating gate conductive film is a double film composed of an amorphous polysilicon film containing no impurities and a polysilicon film containing impurities. Form.

After the trench is formed, a radical oxidation process may be performed before the device isolation layer is formed to remove the damage of the device during the trench etching process.

The device isolation layer may include filling the trench with an insulation layer for insulating the device, performing a heat treatment process to increase the density of the insulation layer for insulation, and performing a planarization process to expose the upper portion of the floating gate. Include.

The insulating layer for device isolation may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or spin on glass (SOG).

The sidewall is formed by forming an insulating film on the entire structure including the device isolation layer, and then performing a dry etching process to leave the insulating layer on the sidewall of the conductive film for the floating gate. The insulating film is formed of an oxide film formed by atomic layer deposition. The insulating film is a source gas, and a silicon source uses SixClx based, SixHx based, SiHxClx based, or HSi [N (CH3) 2] 3, and an oxygen source. Form using H2O or O2. The insulating film is formed to a thickness of 50 to 500 kPa in the temperature range of 100 ~ 800 ℃, 0.1 ~ 1000 Torr pressure range.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 to 7 are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

A method of manufacturing a flash memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3 to 7 as follows.

Referring to FIG. 3, the tunnel oxide film 101 and the floating gate conductive film 102 are sequentially formed on the semiconductor substrate 100. The floating gate conductive film 102 is preferably formed of a double film composed of an amorphous polysilicon film containing no impurities and a polysilicon film containing impurities. Thereafter, the floating gate conductive film 102 and the tunnel oxide film 101 are selectively etched by a dry etching process using an element isolation mask, and then the semiconductor substrate (using the selectively etched floating gate conductive film 102 as a mask). 100 is etched to form trench 103. The device isolation mask is preferably formed of a buffer oxide film and a pad nitride film. The buffer oxide film is intended to prevent damage to the floating gate conductive film 102 due to phosphoric acid in a subsequent mask removal process.

Thereafter, an oxidation process is performed to remove damage to the device generated during the trench etching process. The oxidation process is preferably carried out in a radical oxidation process, since in general dry and wet oxidation, reoxidation of the conductive film 102 for the floating gate may occur.

After the insulating film is formed over the entire structure to fill the trench 103, the insulating film is planarized to expose the upper portion of the floating gate conductive film 102. For example, a CMP process is performed to form the device isolation film 104 in the trench 103. Form. The insulating film is preferably formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or spin on glass (SOG). It is preferable to increase the density of the insulating film by performing a heat treatment step after forming the insulating film before the CMP process.

Thereafter, a wet etching process is performed to lower the EFH of the device isolation layer 104. At this time, in order to prevent the tunnel oxide film 101 from being attacked during the wet etching process, the EFH is lowered to be higher than the top of the tunnel oxide film 101.

Referring to FIG. 4, an insulating film 105 is formed on the entire structure of the semiconductor substrate 100 including the floating gate conductive film 102. The insulating film 105 is preferably formed of an oxide film formed by atomic layer deposition. The oxide film formed by the atomic layer deposition method has an etching rate value similar to that of the oxide deposited by the general low pressure chemical vapor deposition or the plasma deposition method in the dry etching process, but the wet etching rate with respect to the oxide etchant is 2 to 10. Etch rate is about twice as fast. The oxide film formed by the atomic layer deposition method has a lower refractive index than the general oxide film. In other words, the oxide film of the conventional low pressure chemical vapor deposition method shows a refractive index of about 1.45 ~ 1.46, while the refractive index of the oxide film deposited by the present invention shows a value lower than 1.45. That is, the density of the film is inferior to that of the film formed by general low pressure chemical vapor deposition. Therefore, the oxide film formed by the atomic layer deposition method has an etching rate about 2 to 10 times faster than the general oxide film during the wet etching process. The insulating film 105 is a source gas, and the silicon source uses SixClx series, SixHx series, SiHxClx series, or HSi [N (CH3) 2] 3, the oxygen source uses H2O or O2, and the reaction activation energy of the source is used. Catalysts can be used to reduce. Deposition temperature is carried out in the range of 100 ~ 800 ℃, pressure is preferably carried out in the range of 0.1 ~ 1000 Torr. Moreover, it is preferable to form the thickness of an insulating film in 50-500 GPa.

Thereafter, the dry etching process is performed to form the sidewalls 105 by leaving the insulating film 105 in the conductive film 102 for the floating gate.

Referring to FIG. 5, the device isolation layer 104 is partially etched using the floating gate conductive layer 102 and the side wall 105 as a mask so that the upper portion of the device isolation layer has an uneven shape. In the etching process, it is preferable that the device isolation film 104 be etched from 50 μs to 1000 μs.

Referring to FIG. 6, the side wall 105 is removed by performing an etching process. The etching process removes sidewalls 105 using a wet etching process. The wet etching process is preferably formed using BOE and HF. Since the side wall 105 has an etching rate of 2 to 10 times larger than that of the device isolation layer 104, the side wall 105 may be removed by minimizing damage to the device isolation layer 104.

Thereafter, the etching process is performed to widen the opening of the device isolation layer 104, and to expose the upper portion of the device isolation layer 104 remaining on the sidewall of the floating gate conductive layer 102. The height of the side wall of the c) increases. This increases the coupling ratio of the device.

Referring to FIG. 7, the dielectric film 109 is formed on the entire structure of the semiconductor substrate 100 including the floating gate conductive film 102. The dielectric film 109 may be formed in an ONO structure in which the first oxide film 106, the nitride film 107, and the second oxide film 108 are sequentially stacked. Thereafter, a conductive gate conductive film 110 is formed on the dielectric film 109. The control film conductive film 110 is preferably formed of a polysilicon film. As a result, the dielectric film 109 and the control gate conductive film 110 are completely embedded between the floating gate conductive films 102 and spaced apart from each other between the floating gate conductive films 102. It is possible to improve the interference effect between the 102.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, the coupling ratio is increased by increasing the height of the floating gate protruding to the outside of the device isolation layer, and a control gate that is subsequently formed by etching a portion of the device isolation layer between the floating gates is interposed between the floating gates. By forming in the position, the interference effect is reduced, and when etching a portion of the device isolation layer, dry etching is performed by using the spacer to etch the device separation membrane to the desired height, and then the spacer is removed by wet etching. In addition, the device isolation layer formed on the sidewall of the floating gate may be protected.

Claims (11)

Forming a tunnel oxide film and a floating gate conductive film on the semiconductor substrate, and then etching the floating gate conductive film, the tunnel oxide film, and a portion of the semiconductor substrate to form a trench; Forming an isolation layer by filling an insulating layer in the trench and then etching an upper end portion of the isolation layer to adjust the EFH of the isolation layer; Forming a sidewall on a sidewall of the conductive film for the floating gate and then etching an upper end portion of the device isolation layer to an area under the tunnel oxide film; Performing a wet etching process to remove the sidewall; And Forming a dielectric film and a conductive film for a control gate over the entire structure; The sidewall has a wet etching rate higher than that of the device isolation layer in the wet etching process. The method of claim 1, The sidewall has a wet etch rate of 2 to 10 times that of the device isolation layer. The method of claim 1, And each of the floating gate conductive film and the control gate conductive film is formed of a polysilicon film. The method of claim 1, And the conductive film for floating gate is formed of a double layer consisting of an amorphous polysilicon film containing no impurities and a polysilicon film containing impurities. The method of claim 1, After the trench is formed, before the device isolation layer is formed. A method of manufacturing a flash memory device further comprising the step of performing a radical oxidation process to remove the damage of the device generated during the trench etching process. The method of claim 1, Filling the trench with an insulating film for separating a device; Performing a heat treatment process to increase the density of the insulating film for device isolation; And And performing a planarization process to expose the upper portion of the floating gate. The method of claim 6, The insulating layer for isolation of the device is a method of manufacturing a flash memory device formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or spin on glass (SOG). The method of claim 1, And forming the insulating layer on the entire structure including the device isolation layer, and then performing a dry etching process to leave the insulating layer on the sidewall of the conductive layer for the floating gate. The method of claim 8, And the insulating film is formed of an oxide film formed by an atomic layer deposition method. The method of claim 8, Wherein the insulating layer is a source gas, and a silicon source is formed of SixClx, SixHx, SiHxClx, or HSi [N (CH 3) 2] 3, and an oxygen source is formed using H 2 O or O 2. The method of claim 8, The insulating film is a method of manufacturing a flash memory device to form a thickness of 50 ~ 500 kPa in the temperature range of 0.1 ~ 1000 Torr in the temperature range of 100 ~ 800 ℃.

Images