KR20080061517A - A nonvolatile memory device and method of manufacturing the same - Google Patents

Abstract

A nonvolatile memory device and a method of manufacturing the same are provided to increase a distance between floating gates by forming a narrow lower part of the floating gate using a spacer. An active area and an isolation area are defined in a semiconductor substrate. A gate insulating layer(104) is formed in the active area, and an isolation layer(108) is formed in the isolation area. A first conductive layer for floating gate(110) is formed above the gate insulating layer between isolation layers, and has a narrower width than the distance of the isolation layers. A second conductive layer for floating gate(114) is formed above the first conductive layer and has a wider width than the first conductive layer. A dielectric layer and a conductive layer for control gate are formed above the second conductive layer and the isolation layer.

Description

A nonvolatile memory device and method of manufacturing the same

1A through 1H are cross-sectional views sequentially illustrating a nonvolatile memory device and a method of manufacturing the same according to the present invention.

<Description of the symbols for the main parts of the drawings>

102 semiconductor substrate 104 gate insulating film

106: etch stop film 108: device isolation film

110: first conductive film 112 for floating gate: first spacer

114: second conductive film for floating gate 116: second spacer

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device and a method of manufacturing the same that can prevent the interference effect (cell interference).

Among nonvolatile memory devices, NAND type flash memory devices are widely used because they are relatively easy to integrate, compared with other memory devices. The NAND type flash memory device includes a plurality of cell blocks, which include drain select lines, word lines, and source select lines that intersect the active region. (source select lines) A junction region is formed in the active region between the select lines and the word lines. The select line and the word line include a tunnel oxide, a floating gate, a dielectric layer, and a control gate, and the select line and the control gate are electrically connected to each other.

Recently, as the size of a NAND flash memory device is gradually reduced and the distance between cells is shortened, the state of the cell is affected by the operation of adjacent neighboring cells. That is, as the distance between the floating gates is narrowed, the operation of adjacent floating gates is affected, and in particular, the distance between the floating gates of a portion lower than the height of the device isolation layer is mainly affected. The change in the threshold voltage of the cell due to the operation of adjacent neighboring cells, in particular the program operation, is called an interference effect. That is, the interference effect means that when a second cell adjacent to the first cell to be read is programmed, due to a capacitance action caused by a charge change of the floating gate of the second cell, the first cell is read out of the first cell. The threshold voltage higher than the threshold voltage is read. Although the charge of the floating gate of the read cell does not change, it refers to a phenomenon in which the state of the actual cell is distorted by the state change of the adjacent cell. This interference effect causes the state of the cell to change, which results in an increase in the defective rate resulting in a lower yield.

Accordingly, a technique of lowering the height of the floating gate has been introduced to reduce the interference effect, but in this case, the interface area between the control gate and the floating gate is reduced, thereby reducing the coupling ratio. This causes a problem that the speed of programming the cell is reduced.

The present invention increases the distance between the floating gates by narrowing the width of the bottom of the floating gate, and forms a groove on the device isolation layer to form a dielectric film and a control gate in the groove, thereby reducing the interference effect between cells. Can increase the speed.

In the nonvolatile memory device according to the present invention, a gate insulating film is formed in an active region and a device isolation film is formed in an element isolation region, and is formed on an upper portion of the gate insulating film between the device isolation layers, and is less than a distance between the device isolation layers. A first conductive film having a narrow width, a second conductive film for a floating gate formed on an upper portion of the first conductive film for the floating gate, and having a wider width than the first conductive film for the floating gate, and the device isolation layer and the floating layer It may include a dielectric film formed on the gate second conductive film and a conductive film for the control gate.

The insulating layer spacer may be further formed on both sides of the first conductive layer for the floating gate. Both sides of the second conductive layer for the floating gate may contact a portion of the device isolation layer. The second conductive layer for the floating gate may be formed only on the first conductive layer for the floating gate and the insulating layer spacer. The height of the first conductive layer for the floating gate may be higher than the height of the device isolation layer. Grooves may be formed on the device isolation layer.

According to another aspect of the present invention, there is provided a method of fabricating a nonvolatile memory device, the method including: providing a semiconductor substrate having a gate insulating film formed in an active region and a device isolation film formed in an isolation region; Forming a first conductive film, forming a first spacer on sidewalls of the first conductive film, forming a second conductive film having a wider width than the first conductive film on the first conductive film; The method may include forming a dielectric film on the device isolation layer including the second conductive film and forming a conductive film for a control gate on the dielectric film.

Both sides of the second conductive layer may be formed to contact a part of the device isolation layer. The second conductive layer may be formed only on the first conductive layer and the first spacer.

The height of the first conductive layer may be higher than the height of the device isolation layer. The first spacer may be formed of an insulating film.

After forming the second conductive layer, forming a second spacer on a sidewall of the second conductive layer so that a portion of the upper portion of the device isolation layer is exposed and partially removing the exposed upper portion of the device isolation layer using the second spacer. It may further comprise a step. The second spacer may be formed of a nitride film.

The first conductive layer and the second conductive layer may be formed of polysilicon. The first conductive layer and the second conductive layer may serve as floating gates.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1A through 1H are cross-sectional views sequentially illustrating a nonvolatile memory device and a method of manufacturing the same according to the present invention.

Referring to FIG. 1A, a screen oxide (not shown) is formed on a semiconductor substrate 102 formed of silicon. The screen oxide layer prevents the surface of the semiconductor substrate 102 from being damaged during a well ion implantation process or a threshold voltage ion implantation process performed in a subsequent process. Here, the well ion implantation process is performed to form a well region in the semiconductor substrate 102, and the threshold voltage ion implantation process is performed to adjust the threshold voltage of a semiconductor device such as a transistor. As a result, a well region (not shown) may be formed in the semiconductor substrate 102, and the well region may be formed in a triple structure.

After removing the screen oxide layer, the gate insulating layer 104 and the etch stop layer 106 are formed on the semiconductor substrate 102. Preferably, the gate insulating film 104 is formed of an oxide film and may serve as a tunnel oxide film. In addition, the etch stop film 106 is formed of a nitride film. In this case, according to the thickness of the etch stop layer 106, the height at which the device isolation layer formed in a subsequent process may protrude higher than the semiconductor substrate 102 may be adjusted. Therefore, in consideration of this, it is preferable to adjust the thickness of the etch stop layer 106.

Referring to FIG. 1B, a mask pattern (not shown) is formed on the etch stop layer 106. The mask pattern is formed on the etch stop layer 106 corresponding to the active region so that the device isolation region is opened. Preferably, the mask pattern may be formed using a photoresist.

Subsequently, the etch stop film 106 and the gate insulating film 104 are patterned using a mask pattern, and a portion of the semiconductor substrate 102 is subsequently removed to form trenches in the device isolation region of the semiconductor substrate 102. After the mask pattern is removed, an insulating film, for example, an oxide film is formed over the entire structure of the semiconductor substrate 102 including the trench to gap fill the trench. Subsequently, a planarization process such as a chemical mechanical polishing (CMP) method is performed on the upper portion of the insulating layer to form the device isolation layer 108. In this case, the etch stop layer 106 serves as an etch stopper during the planarization process.

Referring to FIG. 1C, the gate insulating layer 104 is exposed by removing the etch stop layer 106 (see FIG. 1B). After forming a conductive film, for example, polysilicon, over the entire structure of the semiconductor substrate 102, an etching process is performed such that the conductive film remains only on the exposed gate insulating film 104. 110). The upper height of the first conductive layer 110 for the floating gate is higher than the upper height of the device isolation layer 108 and lower than the height of the floating gate to be finally formed. In addition, the width of the first conductive layer 110 for the floating gate is smaller than the gap between the device isolation layers 104, so that a predetermined gap exists between the first conductive layer 110 for the floating gate and the device isolation layers 108 on both sides. do.

Referring to FIG. 1D, an insulating film, for example, an oxide film is formed on the entire structure of the semiconductor substrate 102 including the first conductive film 110 for floating gate. In particular, the insulating film is formed so as to completely gap fill the gap between the floating conductive first conductive film 110 and the device isolation film 108 on both sides. The first spacer 112 is formed by removing the remaining insulating film so that the insulating film remains only on the side surface of the first conductive film 110 for floating gate.

Referring to FIG. 1E, a conductive film, for example, polysilicon is formed on the entire structure of the semiconductor substrate 102 including the first conductive film 110 and the first spacer 112 for the floating gate. The conductive film is etched to remain on the first conductive film 110 for the floating gate to form the second conductive film 114 for the floating gate. The width of the second conductive layer 114 for the floating gate is greater than the width of the first conductive layer 110 for the floating gate. In this case, both sides of the second conductive layer 114 for the floating gate may be formed to be in contact with a portion of the device isolation layer 108. As shown in FIG. 1E, the first conductive layer 110 and the first layer for the floating gate 110 may be formed. The second conductive layer 114 for the floating gate may be formed only on the spacer 112. Thus, the second conductive film 114 for the floating gate is electrically connected to the first conductive film 110 for the floating gate to connect the first conductive film 110 for the floating gate and the second conductive film 114 for the floating gate. A floating gate comprising is formed.

According to the present invention, the distance between the floating gates of portions lower than the height of the isolation layer 108 may be further increased due to the first spacers 112 formed of insulating films on both sides of the first conductive layer 110 for floating gates. . As a result, the inter-cell interference effect may be effectively reduced as the distance between the floating gates at a portion lower than the height of the device isolation layer increases.

Referring to FIG. 1F, after the nitride film is formed over the entire structure of the semiconductor substrate 102 including the floating gates 110 and 114, the nitride film is etched to remain only on the sidewalls of the floating gates 110 and 114 to form a second spacer. 116 is formed. In particular, the nitride film formed in the center of the device isolation layer 108 is removed due to the thickness difference in which the nitride film is etched to expose the center of the device isolation layer 108.

Referring to FIG. 1G, a portion of the device isolation layer 108 exposed by using the second spacer 116 is removed to form a groove 118 on the device isolation layer 108.

Referring to FIG. 1H, the second spacer 116 (see FIG. 1G) is removed. Subsequently, although not shown, a dielectric film and a conductive film for the control gate are formed on the device isolation layer 108 and the floating gates 110 and 114 and then etched to complete the manufacture of the nonvolatile memory device.

According to the nonvolatile memory device and a method of manufacturing the same according to the present invention, the floating gate is formed by dividing the upper and lower portions, but the distance between the floating gates can be increased by narrowing the width of the lower portion of the floating gate using spacers. In addition, by forming a groove on the device isolation layer to form a dielectric film and a control gate in the groove can reduce the interference effect between cells. As a result, a high-performance nonvolatile memory device can be manufactured by increasing a speed of programming a cell.

Claims (15)

A semiconductor substrate having a gate insulating film formed in the active region and a device isolation film formed in the device isolation region; A first conductive layer formed over the gate insulating layer between the device isolation layers, the first conductive layer having a width smaller than the distance between the device isolation layers; A second conductive film for floating gate formed on the first conductive film for the floating gate and wider than the first conductive film for the floating gate; And And a dielectric layer formed on the device isolation layer, the second conductive layer for the floating gate, and a conductive layer for the control gate. The method of claim 1, And a dielectric spacer formed on both sides of the first conductive layer for the floating gate. The method of claim 1, Both sides of the second conductive film for the floating gate is in contact with a portion of the device isolation film. The method of claim 2, The second conductive layer for the floating gate is formed only on the first conductive layer for the floating gate and the insulating layer spacer. The method of claim 1, The height of the first conductive layer for the floating gate is higher than the height of the device isolation layer. The method of claim 1, And a groove formed on the device isolation layer. Providing a semiconductor substrate having a gate insulating film formed in the active region and a device isolation film formed in the device isolation region; Forming a first conductive film on the gate insulating film between the device isolation films; Forming a first spacer on sidewalls of the first conductive film; Forming a second conductive film having a width wider than that of the first conductive film on the first conductive film; Forming a dielectric film on the device isolation layer including the second conductive film; And And forming a control gate conductive film on the dielectric film. The method of claim 7, wherein Both sides of the second conductive film is formed to be in contact with a portion of the device isolation film manufacturing method of a nonvolatile memory device. The method of claim 7, wherein The second conductive layer is formed only on the first conductive layer and the first spacer. The method of claim 7, wherein And a height of the first conductive layer is higher than that of the device isolation layer. The method of claim 7, wherein The first spacer is formed of an insulating film. The method of claim 7, after forming the second conductive film, Forming a second spacer on a sidewall of the second conductive layer to expose a portion of an upper portion of the device isolation layer; And And removing a portion of the exposed upper portion of the device isolation layer using the second spacer. The method of claim 12, And the second spacer is formed of a nitride film. The method of claim 7, wherein The first conductive film and the second conductive film are formed of polysilicon. The method of claim 7, wherein The first conductive layer and the second conductive layer serve as a floating gate.

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