KR20080061151A - Method of manufacturing a flash memory device - Google Patents

Abstract

A method for fabricating a flash memory device is provided to reduce the cross section of polysilicon constituting a floating gate by including a floating gate having an I shape. A tunnel insulation layer(101) and a first conductive layer(102) for a floating gate are sequentially formed on a semiconductor substrate(100). The first conductive layer for the floating gate, the tunnel insulation layer and the semiconductor substrate are etched by a predetermined depth to form a trench. The trench is filled with an insulation layer to form an isolation layer(104). Both edges of the upper part of the first conductive layer for the floating gate are etched to be a convex pattern. After an insulation layer is formed on the resultant structure, a planarization process is performed to expose the upper end of the first conductive layer for the floating gate. A second conductive layer for the floating gate is formed on the resultant structure and is patterned to form a floating gate of an I shape. A dielectric layer(113) and a conductive layer(114) for a control gate are sequentially formed on the I-shaped floating gate. The first and second conductive layers can be made of polysilicon layers.

Description

Method of manufacturing a flash memory device

1 is a cross-sectional view of a device for explaining a method of manufacturing a flash memory device according to the prior art.

2 is a graph illustrating a relationship between an interference ratio and a coupling ratio according to a height of a floating gate and a distance between floating gates of a flash memory device.

3 to 10 are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 101 tunnel insulating film

102: first conductive film 103 for floating gate: trench

104: device isolation film 105, 106: photoresist pattern

107: insulating film 108: second conductive film for floating gate

109: hard mask pattern 110: the first oxide film

111 nitride film 112 second oxide film

113 dielectric film 114 conductive film for control gate

The present invention relates to a flash memory device, and more particularly to a method of forming a floating gate of a flash memory device that can reduce the inter-cell interference.

In a NAND type flash memory device, a plurality of cells for storing data are connected in series to form a string, and a drain select transistor and a source select transistor are formed between the cell string and the drain and the cell string and the source, respectively. A cell of such a NAND flash memory device is formed by forming a gate in which a tunnel insulating film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on a semiconductor substrate, and forming junctions on both sides of the gate.

In such a NAND flash memory device, it is very important to keep the cell state constant because the state of the cell is affected by the operation of adjacent neighboring cells. The change of the state of the cell due to the operation of adjacent neighboring cells, in particular the program operation, is called an interference effect. That is, the interference effect means that when the second cell adjacent to the first cell to be read is programmed, the threshold voltage of the first cell is higher than the threshold voltage of the first cell when the first cell is read due to the capacitance action caused by the charge change of the floating gate of the second cell. It refers to a phenomenon in which the threshold voltage is read, and refers to a phenomenon in which the state of the actual cell is distorted due to the change of state of the adjacent cell, although the charge of the floating gate of the read cell does not change. This interference effect causes the state of the cell to change, which results in an increase in the defective rate resulting in a lower yield. Therefore, minimizing the interference effect can be said to be effective to keep the state of the cell constant.

Meanwhile, a part of the device isolation layer and the floating gate are formed by using a self-aligned shallow trench isolation (SA-STI) process in a manufacturing process of a general NAND flash memory device. Referring to FIG. Is the same as

After the tunnel insulating film 11 and the first polysilicon film 12 are formed on the semiconductor substrate 10, predetermined regions of the first polysilicon film 12 and the tunnel insulating film 11 are etched to form a semiconductor substrate 10. ) To form a trench 13 by etching to a predetermined depth, the insulating film is buried and a polishing process is performed to form the device isolation film 14. Thereafter, the first oxide film 15, the nitride film 16, and the second oxide film 17 are sequentially formed to form the dielectric film 18.

When the flash memory device is manufactured using the SA-STI process as described above, since the device isolation layer is formed between the first polysilicon layer and the first polysilicon layer adjacent to the floating polysilicon layer, the first polysilicon layer is formed between the first polysilicon layers. Interference may occur in the.

2 is a graph showing the interference effect and the coupling ratio according to the height and distance between the floating gates.

Referring to FIG. 2, the gate-to-gate interface is proportional to the distance between the floating gates and the height of the floating gates. That is, if the distance between the floating gates is far and the height of the floating gate decreases, the interference decreases. On the contrary, when the height of the floating gate is decreased, the interface area between the floating gate and the control gate is decreased, thereby reducing the coupling ratio.

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a flash memory device capable of reducing inter-cell interference by reducing the cross-sectional area of polysilicon constituting the floating gate by forming the floating gate of the flash memory device in an I-shape. There is.

A method of manufacturing a flash memory device according to an embodiment of the present invention comprises the steps of sequentially forming a tunnel insulating film and a first conductive film for a floating gate on a semiconductor substrate, the first conductive film for the floating gate, the tunnel insulating film, and Etching the semiconductor substrate to a predetermined depth to form a trench; forming a device isolation layer by filling the trench with an insulating layer; and etching both edges of an upper end portion of the first conductive layer for the floating gate to form an iron pattern. And forming an insulating film on the entire structure including the first conductive film for the floating gate, and then performing a planarization process to expose an upper end portion of the first conductive film for the floating gate, and including the insulating film. After forming the second conductive film for the floating gate on the entire structure and patterning the I-shaped floating gay Forming, and forming an I-shaped film as dielectric film and a control gate on the floating gate for the challenge in order.

An upper end of the first conductive layer for the floating gate is etched and an upper end of the isolation layer is etched to reduce the EHF of the isolation layer. In the etching of the upper end of the first conductive layer for the floating gate, each width of each of the edges to be etched is 1/3 to 1/2 of the total width. The thickness of the lower end of the first conductive film for floating gate of the iron pattern is 100 to 150 kPa. The thickness of the second conductive film for the floating gate is 200 to 300 mW. The device isolation film is an HDP oxide film, and the first conductive film for the floating gate and the second conductive film for the floating gate are formed of a polysilicon film. The dielectric film is an ONO structure dielectric film composed of a first oxide film, a nitride film, and a second oxide film.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

3 to 10 are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 3, the tunnel insulating layer 101 and the floating conductive first conductive layer 102 are sequentially formed on the semiconductor substrate 100. The first conductive film 102 for the floating gate is preferably formed of a polysilicon film. Thereafter, the first conductive film 102 and the tunnel insulating film 101 for the floating gate are selectively etched by an etching process using an element isolation mask, and then the first conductive film 102 and the tunnel insulating film for the selectively etched floating gate are etched. The trench 103 is formed by etching the semiconductor substrate 100 using 101 as a mask.

Referring to FIG. 4, an insulating film, such as an HDP oxide film, is formed over the entire structure to fill the trench 103, and then the insulating film is planarized to expose the upper portion of the first conductive film 102 for floating gate, for example, to perform a CMP process. The device isolation film 104 is formed in the trench 103.

Referring to FIG. 5, one region of the first conductive layer 102 for the floating gate is etched by an etching process using the photoresist pattern 105. The etched region of the first conductive film 102 for the floating gate is one edge of the first conductive film 102 for the floating gate and is larger than 1/3 of the width of the first conductive film 102 for the entire floating gate. Less than 2 In this case, a portion of the device isolation layer 104 may be etched together. Thereafter, the string process is performed to remove the photoresist pattern 105.

Referring to FIG. 6, the other end region of the first conductive layer 102 for the floating gate is etched by an etching process using the photoresist pattern 106. The etched region of the first conductive film 102 for the floating gate is the opposite edge of the etched region in FIG. 5 of the first conductive film 102 for the floating gate, and is the width of the first conductive film 102 for the entire floating gate. Greater than 1/3 and less than 1/2 At this time, the protrusions of the remaining device isolation layer 104 are also etched to lower the EFH of the device isolation layer 104. Thereafter, the string process is performed to remove the photoresist pattern 105. For this reason, the first conductive film 102 for floating gate is formed in the pattern of iron. In this case, the etching process of the first conductive film 102 for floating gate is preferably formed so that the thickness of the first conductive film 102 for floating gate remaining on the bottom portion is 100 to 150 kPa.

Referring to FIG. 7, an insulating film 107 is formed over the entire structure including the first conductive film 102 for floating gates having an iron pattern. The insulating film 107 is preferably formed of an oxide film. Thereafter, the CMP process is performed to planarize the insulating film 107 so that the upper portion of the first conductive film 102 for the floating gate is exposed.

Referring to FIG. 8, the second conductive layer 108 for the floating gate is formed on the entire structure including the insulating layer 107. The second conductive film 108 for the floating gate is preferably formed of a polysilicon film. The second conductive film 108 for the floating gate is preferably formed to a thickness of 200 to 300 kPa.

Referring to FIG. 9, an etching process using the hard mask pattern 109 is performed to pattern the second conductive layer 108 for the floating gate to pattern the second conductive layer 108 for the floating gate and the first conductive layer for the floating gate. A floating gate consisting of 102 is formed. Thus, the floating gate is formed in an I-shaped pattern in which the width of the interruption portion is larger than the upper and lower portions. The distance between the portions where the inter-cell interference occurs is relatively large, thereby reducing the interference effect.

Referring to FIG. 10, the dielectric film 113 including the first oxide film 110, the nitride film 111, and the second oxide film 112 is formed on the entire structure including the I-shaped floating gates 102 and 108. do. Thereafter, the control gate conductive film 114 is formed over the entire structure including the dielectric film 113.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, by forming the floating gate of the flash memory device in an I-shape, the cross-sectional area of the polysilicon constituting the floating gate may be reduced to reduce the inter-cell interference.

Claims (8)

Sequentially forming a tunnel insulating film and a first conductive film for floating gate on the semiconductor substrate; Etching the first conductive layer for the floating gate, the tunnel insulating layer, and the semiconductor substrate to a predetermined depth to form a trench; Filling the trench with an insulating layer to form an isolation layer; Etching both edges of an upper end portion of the first conductive layer for the floating gate to form an iron pattern; Forming an insulating film on the entire structure including the first conductive film for the floating gate, and then performing a planarization process to expose an upper end portion of the first conductive film for the floating gate; Forming an I-shaped floating gate by forming and then patterning a second conductive film for a floating gate on the entire structure including the insulating film; And And sequentially forming a dielectric film and a conductive film for a control gate on the I-shaped floating gate. The method of claim 1, And etching the upper end of the first conductive layer for the floating gate and etching the upper end of the device isolation layer to reduce the EHF of the device isolation layer. The method of claim 1, Etching the upper end portion of the first conductive layer for the floating gate, wherein each width of each of the edges to be etched is 1/3 to 1/2 of the total width. The method of claim 1, And a thickness of the lower end portion of the first conductive film for the floating gate of the iron pattern is 100 to 150 microseconds. The method of claim 1, And a thickness of the second conductive film for the floating gate is 200 to 300 mW. The method of claim 1, The device isolation film is a HDP oxide film manufacturing method of a flash memory device. The method of claim 1, The first conductive film for the floating gate and the second conductive film for the floating gate are formed of a polysilicon film. The method of claim 1, And the dielectric film is an ONO structure dielectric film composed of a first oxide film, a nitride film, and a second oxide film.

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