USRE42409E1 - Method of manufacturing flash memory device - Google Patents
Method of manufacturing flash memory device Download PDFInfo
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- USRE42409E1 USRE42409E1 US12/800,858 US80085810A USRE42409E US RE42409 E1 USRE42409 E1 US RE42409E1 US 80085810 A US80085810 A US 80085810A US RE42409 E USRE42409 E US RE42409E
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 239000007943 implant Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the invention relates, in general, to flash memory devices and, more particularly, to a method of manufacturing a flash memory device in which interference between floating gates can be reduced and the coupling ratio can be increased.
- a NAND flash memory device In a NAND flash memory device, a plurality of cells for storing data are connected in series to form one string. A drain select transistor and a source select transistor are formed between the cell string and the drain and between the cell string and the source, respectively.
- a gate in which a tunnel oxide layer, a floating gate, a dielectric layer and a control gate are stacked is formed at a specific region on a semiconductor substrate. Junctions are formed at both sides of the gate.
- the state of the cell is influenced by the operation of neighboring cells. It is therefore very important to maintain a constant cell state.
- a phenomenon in which the state of the cell is changed due to the operation of neighboring cells i.e., a program operation
- an interference phenomenon A phenomenon in which the state of the cell is changed due to the operation of neighboring cells (i.e., a program operation) is called an interference phenomenon.
- a second cell adjacent to a first cell to be read is programmed, a threshold voltage higher than that of the first cell is read due to a capacitance phenomenon caused by a change in the charges of the floating gate of the second cell. Therefore, although the charge of the floating gate of the first cell is not changed, the actual state of the first cell appears distorted due to a change in the state of neighboring cells.
- the state of the cell is changed due to the interference phenomenon, resulting in a degraded yield of the failure ratio. Accordingly, it is desirable to maintain a constant cell state by minimizing the interference phenomenon.
- SA-STI Self-Aligned Shallow Trench Isolation
- a tunnel oxide layer 11 and a first polysilicon layer 12 are formed over a semiconductor substrate 10 . Specific regions of the first polysilicon layer 12 and the tunnel oxide layer 11 are etched. The semiconductor substrate 10 is etched to a specific depth, forming trenches. The trenches are filled with an insulating layer. A polish process is then performed to form isolation layers 13 in the trenches. Thereafter, a second polysilicon layer 14 is formed and then etched to form floating gates 12 and 14 . A dielectric layer 15 and a third polysilicon layer 16 for a control gate are formed over the floating gates 12 and 14 .
- the flash memory device is fabricated by the SA-STI process described above, interference may occur between the first polysilicon layers 12 because the isolation layers 13 are formed between neighboring first polysilicon layers 12 serving as the floating gates.
- FIG. 2 is a graph illustrating the floating gate interference coupling ratio as a function of floating gate height and the gate-to-gate distance between floating gates of a flash memory device.
- inter-gate interference is inversely proportional to the distance between the floating gates and proportional to the height of the floating gate. In other words, if the distance between the floating gates increases and the height of the floating gate decreases, interference is reduced. However, if the height of the floating gate decreases, the interface area of the floating gate and the control gate is reduced and the coupling ratio is reduced.
- the invention addresses the above problems and provides a manufacturing method for a flash memory device.
- a floating gate is partially etched to have a U-shaped form so that the interfacial area between the floating gate and a control gate can be increased and the coupling ratio can be increased accordingly.
- a portion of an isolation layer between the floating gates is etched so that the control gate to be formed subsequently is disposed between the floating gates, thereby reducing the interference phenomenon.
- a method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form the trenches, filling the trenches with an insulating layer to form isolation layers projecting above the floating gate, forming spacers sidewalls of the isolation layers projecting above the floating gate, etching the conductive layer using the spacers as a mask, thereby forming a U-shaped conductive layer, removing the spacers, etching the top surface of the isolation layers, thereby controlling an Effective Field Height (EFH) of the isolation layer, and forming a dielectric layer and a second conductive layer for a control gate on the resulting surface.
- ESH Effective Field Height
- FIG. 1 is a cross-sectional view illustrating a conventional method of manufacturing a flash memory device
- FIG. 2 is a graph illustrating the floating gate interference coupling ratio as a function of floating gate height and distance between floating gates of a flash memory device
- FIGS. 3 to 8 are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the invention.
- FIGS. 3 to 8 are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the invention.
- a wall formation ion implant process and an ion implant process for controlling the threshold voltage are performed on a semiconductor substrate 100 .
- a tunnel oxide layer 101 , a conductive layer 102 for a floating gate, a buffer oxide layer 103 , a nitride layer 104 for a hard mask are sequentially formed over the semiconductor substrate 100 .
- the conductive layer 102 can be formed of a polysilicon layer.
- the buffer oxide layer 103 protects the conductive layer 102 when removing the nitride layer 104 .
- the buffer oxide layer 103 , the conductive layer 102 , and the tunnel oxide layer 101 are selectively etched by using an etch process using the nitride layer 104 as a mask.
- the semiconductor substrate 100 is etched to form trenches 105 .
- An insulating layer such as a high density plasma (HDP) oxide layer, is formed on the entire surface so that the trenches 105 are filled.
- a polishing process such as a chemical-mechanical polish (CMP) is performed on the insulating layer such that the nitride layer 104 is exposed, thereby forming isolation layers 106 within the trenches 105 .
- CMP chemical-mechanical polish
- an etch process is performed to remove the nitride layer 104 . Thereafter, an oxide layer 107 is formed above the entire resulting structure of the semiconductor substrate 100 including the isolation layer 106 and the conductive layer 102 .
- the oxide layer 107 is preferably formed to a thickness of 50 Angstrom to 100 Angstrom.
- an etch process is performed to form spacers 108 including a portion of the oxide layer 107 and a portion of the buffer oxide layer 103 remaining only on the side walls of the exposed isolation layer 106 .
- the top surface of the conductive layer 102 is etched by an etch process using the spacers 108 as etch masks, so that the conductive layer 102 has a shape, that is, a U shape.
- the etch process is preferably performed by using HBr/O 2 , HBr/Cl 2 /O 2 or Cl 2 /O 2 having a high selectivity with respect to an oxide layer.
- the thickness of the bottom of the conductive layer 102 (i.e. the distance from the tunnel oxide layer 101 to the bottom of the U-shaped gap defined by the etched conductive layer 102 ) preferably ranges from 300 Angstroms to 500 Angstroms.
- an angle ⁇ formed by an inner sidewall and the bottom of the etched conductive layer 102 is preferably in the range of 91 to 95 degrees.
- an etch process is performed to remove the spacers 108 .
- An oxide layer recess process is then performed in order to lower an Effective Field Height (EFH) of the isolation layer 106 , which can be an oxide layer (e.g., an HDP oxide layer).
- the EFH is preferably within a range of 200 to Angstroms 400 Angstroms.
- a dielectric layer 109 is formed on the entire structure of the semiconductor substrate 100 , including the conductive layer 102 having the U shape.
- the dielectric layer 109 preferably has an oxide-nitride-oxide (ONO) structure in which a first oxide layer, a nitride layer and a second oxide layer are sequentially formed.
- ONO oxide-nitride-oxide
- a conductive layer 110 for a control gate is formed on the dielectric layer 109 .
- the conductive layer 110 is preferably formed of a polysilicon layer.
- the dielectric layer 109 and the conductive layer 110 completely fill the U-shaped gap between opposing sidewalls of the etched conductive layers 102 , so that the opposing sidewalls of the conductive layers 102 are isolated from each other. Accordingly, the interference phenomenon between adjacent conductive layers 102 can be improved.
- a floating gate is partially etched to have a U shape. Accordingly, the interfacial area of the floating gate and a control gate can be increased, the coupling ratio can be increased, and the program speed of a cell can be improved.
- an isolation layer between the floating gates is partially etched so that a control gate to be formed subsequently is disposed between the floating gates. It is therefore possible to reduce the interference phenomenon.
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Abstract
A method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form the trenches, filling the trenches with an insulating layer to form isolation layers projecting above the floating gate, forming spacers on sidewalls of the isolation layers projecting above the floating gate, etching the conductive layer using the spacers as a mask, thereby forming a U-shaped conductive layer, removing the spacers, etching the top surface of the isolation layers, thereby controlling an Effective Field Height (EFH) of the isolation layer, and forming a dielectric layer and a conductive layer for a control gate on the resulting surface.
Description
Priority to Korean patent application number 2006-59522, filed on Jun. 29, 2006, the disclosure of which is incorporated by reference in its entirety, is claimed.
The invention relates, in general, to flash memory devices and, more particularly, to a method of manufacturing a flash memory device in which interference between floating gates can be reduced and the coupling ratio can be increased.
In a NAND flash memory device, a plurality of cells for storing data are connected in series to form one string. A drain select transistor and a source select transistor are formed between the cell string and the drain and between the cell string and the source, respectively. In the cell of the NAND flash memory device, a gate in which a tunnel oxide layer, a floating gate, a dielectric layer and a control gate are stacked is formed at a specific region on a semiconductor substrate. Junctions are formed at both sides of the gate.
In the NAND flash memory device constructed above, the state of the cell is influenced by the operation of neighboring cells. It is therefore very important to maintain a constant cell state. A phenomenon in which the state of the cell is changed due to the operation of neighboring cells (i.e., a program operation) is called an interference phenomenon. In other words, if a second cell adjacent to a first cell to be read is programmed, a threshold voltage higher than that of the first cell is read due to a capacitance phenomenon caused by a change in the charges of the floating gate of the second cell. Therefore, although the charge of the floating gate of the first cell is not changed, the actual state of the first cell appears distorted due to a change in the state of neighboring cells. The state of the cell is changed due to the interference phenomenon, resulting in a degraded yield of the failure ratio. Accordingly, it is desirable to maintain a constant cell state by minimizing the interference phenomenon.
Meanwhile, in a manufacturing process of a general NAND flash memory device, part of the isolation layer and the floating gate is formed using a Self-Aligned Shallow Trench Isolation (SA-STI) process. The process is described below with reference to FIG. 1 .
A tunnel oxide layer 11 and a first polysilicon layer 12 are formed over a semiconductor substrate 10. Specific regions of the first polysilicon layer 12 and the tunnel oxide layer 11 are etched. The semiconductor substrate 10 is etched to a specific depth, forming trenches. The trenches are filled with an insulating layer. A polish process is then performed to form isolation layers 13 in the trenches. Thereafter, a second polysilicon layer 14 is formed and then etched to form floating gates 12 and 14. A dielectric layer 15 and a third polysilicon layer 16 for a control gate are formed over the floating gates 12 and 14.
If the flash memory device is fabricated by the SA-STI process described above, interference may occur between the first polysilicon layers 12 because the isolation layers 13 are formed between neighboring first polysilicon layers 12 serving as the floating gates.
Referring to FIG. 2 , inter-gate interference is inversely proportional to the distance between the floating gates and proportional to the height of the floating gate. In other words, if the distance between the floating gates increases and the height of the floating gate decreases, interference is reduced. However, if the height of the floating gate decreases, the interface area of the floating gate and the control gate is reduced and the coupling ratio is reduced.
Accordingly, the invention addresses the above problems and provides a manufacturing method for a flash memory device. In the method, a floating gate is partially etched to have a U-shaped form so that the interfacial area between the floating gate and a control gate can be increased and the coupling ratio can be increased accordingly. A portion of an isolation layer between the floating gates is etched so that the control gate to be formed subsequently is disposed between the floating gates, thereby reducing the interference phenomenon.
According to an aspect of the invention, a method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form the trenches, filling the trenches with an insulating layer to form isolation layers projecting above the floating gate, forming spacers sidewalls of the isolation layers projecting above the floating gate, etching the conductive layer using the spacers as a mask, thereby forming a U-shaped conductive layer, removing the spacers, etching the top surface of the isolation layers, thereby controlling an Effective Field Height (EFH) of the isolation layer, and forming a dielectric layer and a second conductive layer for a control gate on the resulting surface.
Now, a specific embodiment of the disclosure is described with reference to the accompanying drawings.
Referring to FIG. 3 , a wall formation ion implant process and an ion implant process for controlling the threshold voltage are performed on a semiconductor substrate 100. A tunnel oxide layer 101, a conductive layer 102 for a floating gate, a buffer oxide layer 103, a nitride layer 104 for a hard mask are sequentially formed over the semiconductor substrate 100. The conductive layer 102 can be formed of a polysilicon layer. The buffer oxide layer 103 protects the conductive layer 102 when removing the nitride layer 104. Thereafter, the buffer oxide layer 103, the conductive layer 102, and the tunnel oxide layer 101 are selectively etched by using an etch process using the nitride layer 104 as a mask. The semiconductor substrate 100 is etched to form trenches 105.
An insulating layer, such as a high density plasma (HDP) oxide layer, is formed on the entire surface so that the trenches 105 are filled. A polishing process, such as a chemical-mechanical polish (CMP), is performed on the insulating layer such that the nitride layer 104 is exposed, thereby forming isolation layers 106 within the trenches 105.
Referring to FIG. 4 , an etch process is performed to remove the nitride layer 104. Thereafter, an oxide layer 107 is formed above the entire resulting structure of the semiconductor substrate 100 including the isolation layer 106 and the conductive layer 102. The oxide layer 107 is preferably formed to a thickness of 50 Angstrom to 100 Angstrom.
Referring to FIG. 5 , an etch process is performed to form spacers 108 including a portion of the oxide layer 107 and a portion of the buffer oxide layer 103 remaining only on the side walls of the exposed isolation layer 106.
Referring to FIG. 6 , the top surface of the conductive layer 102 is etched by an etch process using the spacers 108 as etch masks, so that the conductive layer 102 has a shape, that is, a U shape. The etch process is preferably performed by using HBr/O2, HBr/Cl2/O2 or Cl2/O2 having a high selectivity with respect to an oxide layer. Further, the thickness of the bottom of the conductive layer 102, (i.e. the distance from the tunnel oxide layer 101 to the bottom of the U-shaped gap defined by the etched conductive layer 102) preferably ranges from 300 Angstroms to 500 Angstroms. Furthermore, an angle α formed by an inner sidewall and the bottom of the etched conductive layer 102 is preferably in the range of 91 to 95 degrees.
Referring to FIG. 7 , an etch process is performed to remove the spacers 108. An oxide layer recess process is then performed in order to lower an Effective Field Height (EFH) of the isolation layer 106, which can be an oxide layer (e.g., an HDP oxide layer). The EFH is preferably within a range of 200 to Angstroms 400 Angstroms.
Referring to FIG. 8 , a dielectric layer 109 is formed on the entire structure of the semiconductor substrate 100, including the conductive layer 102 having the U shape. The dielectric layer 109 preferably has an oxide-nitride-oxide (ONO) structure in which a first oxide layer, a nitride layer and a second oxide layer are sequentially formed.
A conductive layer 110 for a control gate is formed on the dielectric layer 109. The conductive layer 110 is preferably formed of a polysilicon layer. The dielectric layer 109 and the conductive layer 110 completely fill the U-shaped gap between opposing sidewalls of the etched conductive layers 102, so that the opposing sidewalls of the conductive layers 102 are isolated from each other. Accordingly, the interference phenomenon between adjacent conductive layers 102 can be improved.
As described above, according to the invention, a floating gate is partially etched to have a U shape. Accordingly, the interfacial area of the floating gate and a control gate can be increased, the coupling ratio can be increased, and the program speed of a cell can be improved.
Furthermore, an isolation layer between the floating gates is partially etched so that a control gate to be formed subsequently is disposed between the floating gates. It is therefore possible to reduce the interference phenomenon.
Although the foregoing description has been made with reference to the illustrated embodiments, it is to be understood that changes and modifications may be made by the ordinarily skilled in the art without departing from the spirit and scope of the disclosure and appended claims.
Claims (10)
1. A method of manufacturing a flash memory device, comprising the steps of:
forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate;
etching a portion of the conductive layer, the tunnel oxide layer, and the semiconductor substrate to form trenches;
forming isolation layers at the trenches, wherein the isolation layers project above floating gate;
forming spacers on exposed sidewalls of the isolation layers projecting above the conductive layer;
etching the conductive layer using the spacers as an etch mask, thereby forming a U-shaped conductive layer;
removing the spacers;
etching the top surface of the isolation layers, thereby controlling an Effective Field Height (EFH) of the isolation layer; and
forming a dielectric layer and a second conductive layer for a control gate on the resulting surface.
2. The method of claim 1 , further comprising, before the step of forming the trenches, performing a wall formation ion implant process and an ion implant process for controlling threshold voltage on the semiconductor substrate.
3. The method of claim 1 , wherein the step of forming the trenches comprises the steps of:
sequentially forming the tunnel oxide layer, the conductive layer for the floating gate, a buffer oxide layer, and a nitride layer over the semiconductor substrate;
performing an etch process employing a mask to pattern the nitride layer; thereby forming a hard mask;
performing an etch process using the hard mask, sequentially etching the buffer oxide layer, the conductive layer for the floating gate, and the tunnel oxide layer, thereby exposing a specific region of the semiconductor substrate; and
etching the specific region of the exposed semiconductor substrate to form the trenches.
4. The method of claim 1 , wherein the conductive layer for the floating gate and the second conductive layer for the control gate each comprise a polysilicon layer.
5. The method of claim 1 , wherein the step of forming the spacers comprises the steps of:
forming an oxide layer above the resulting structure of the semiconductor substrate including the isolation layers and the conductive layer for the floating gate; and
performing an etch process to form the spacers such that the oxide layer remains only on sidewalls of the isolation layers projecting above the floating gate.
6. The method of claim 5 , wherein the oxide layer has a thickness of 50 Angstroms to 100 Angstroms.
7. The method of claim 1 , wherein the U-shaped conductive layer comprises a bottom portion having a thickness in a range of 300 Angstroms to 500 Angstroms.
8. The method of claim 1 , wherein the step of etching the conductive layer comprises using an etch gas selected from the group consisting of HBr/O2, HBr/Cl2/O2, and Cl2/O2, wherein the etch gas has a high etch selectivity relative to an oxide.
9. The method of claim 1 , wherein the U-shaped conductive layer comprises a bottom portion and a sidewall, the angle between the bottom portion and the sidewall being in a range of 91 degrees to 95 degrees.
10. The method of claim 1 , wherein the step of etching the top surface of the isolation layers to control the EFH comprises performing an oxide layer recess process so that the resulting EFH of the isolation layer is in the range of 200 Angstroms to 400 Angstroms.
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US12/800,858 USRE42409E1 (en) | 2006-06-29 | 2010-05-24 | Method of manufacturing flash memory device |
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KR1020060059522A KR100870339B1 (en) | 2006-06-29 | 2006-06-29 | Method of manufacturing a flash memory device |
US11/768,722 US7696043B2 (en) | 2006-06-29 | 2007-06-26 | Method of manufacturing a flash memory device |
US12/800,858 USRE42409E1 (en) | 2006-06-29 | 2010-05-24 | Method of manufacturing flash memory device |
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US12/800,858 Expired - Fee Related USRE42409E1 (en) | 2006-06-29 | 2010-05-24 | Method of manufacturing flash memory device |
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KR100780774B1 (en) * | 2006-11-07 | 2007-11-30 | 주식회사 하이닉스반도체 | Nand type non-volatile memory device and method for fabricating the same |
US8193575B2 (en) * | 2008-02-07 | 2012-06-05 | International Business Machines Corporation | Flash memory structure with enhanced capacitive coupling coefficient ratio (CCCR) and method for fabrication thereof |
US9437470B2 (en) * | 2013-10-08 | 2016-09-06 | Cypress Semiconductor Corporation | Self-aligned trench isolation in integrated circuits |
CN104637816B (en) * | 2013-11-11 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | Flash memory cell and preparation method thereof |
CN105789212A (en) * | 2014-12-24 | 2016-07-20 | 上海格易电子有限公司 | Flash memory unit and fabrication method |
US9825046B2 (en) * | 2016-01-05 | 2017-11-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flash memory device having high coupling ratio |
CN110838490A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Preparation method of floating gate memory and floating gate memory |
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Also Published As
Publication number | Publication date |
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US20080003749A1 (en) | 2008-01-03 |
KR20080001266A (en) | 2008-01-03 |
KR100870339B1 (en) | 2008-11-25 |
US7696043B2 (en) | 2010-04-13 |
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