KR20100013939A - Flash memory device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A flash memory device and a manufacturing method thereof are provided to improve an interference effect by forming a floating gate and a control gate with wider width of a lower part than that of an upper part into a horizontal structure. CONSTITUTION: A tunnel insulating layer(102), a laminated layer of a sacrificial insulating layer and a first conductive layer(104) are formed in the active area of a semiconductor substrate(101). The planarized element isolation layer and the laminated layer are formed in an element isolation region of the substrate. The element isolation layer is projected by removing the sacrificial dielectric layer between regions where the floating gate is formed. A spacer exposing a part of the first conductive layer is formed in the sidewall of the projected element isolation layer. A second conductive layer(116) filling the inside of the spacer on the first conductive film exposed is formed. A dielectric film and a control gate(124) are formed along the surface of the first and the second conductive film.

Description

Flash memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same. In particular, a flash memory device having a horizontal gate structure capable of improving an interference effect between cells and preventing a leaning of a gate pattern, and The manufacturing method is related.

In a NAND type flash memory device, a plurality of cells are connected in series between a drain select transistor and a source select transistor to form a string, a drain of the drain select transistor is connected to a bit line, and a source of the source select transistor is Is connected to a common source line. A cell of such a NAND flash memory device is formed by forming a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on a semiconductor substrate, and forming junctions on both sides of the gate.

In the NAND type flash memory device, it is very important to keep the state of the cell constant since the state of the cell is affected by the operation of adjacent neighboring cells. The change of the state of the cell due to the operation of adjacent neighboring cells, in particular the program operation, is called an interference effect. That is, the interference effect means that when the second cell adjacent to the first cell to be read is programmed, the threshold voltage of the first cell when the first cell is read due to a capacitance effect caused by the charge change of the floating gate of the second cell. It refers to a phenomenon in which a threshold voltage higher than the threshold voltage (Vt) is read, and the charge of the floating gate of the read cell does not change, but the state of the actual cell is distorted due to the change of the state of the adjacent cell. This interference effect causes the state of the cell to change, which results in an increase in the defective rate resulting in a lower yield. Therefore, minimizing the interference effect may be effective to keep the state of the cell constant.

Recently, due to the high integration of semiconductor devices, a device isolation layer is formed by using a self-aligned-shallow trench isolation (SA-STI) process in a general NAND type flash memory device manufacturing process. After forming a laminated film of the tunnel oxide film and the first polysilicon film on the semiconductor substrate, the device isolation region of the first polysilicon film and the tunnel oxide film is etched, and the exposed semiconductor substrate is etched to a predetermined depth to form a trench. Subsequently, an insulating film is deposited to fill the trench, and then a planarization process is performed to form a device isolation layer, and the device isolation layer is etched by a predetermined thickness to control the effective field oxide height (EFH). Subsequently, a dielectric film is formed on the device isolation film and the first polysilicon film, and a second polysilicon film is formed on the dielectric film. Thereafter, the second polysilicon film, the dielectric film, the first polysilicon film, and the tunnel oxide film are patterned by a conventional gate etching process, and the control gate including the floating gate made of the first polysilicon film pattern and the second polysilicon film pattern. To form a gate pattern of a tunnel oxide film, a floating gate, a dielectric film, and a control gate stacked structure.

When the device is manufactured in the above manner, the distance between adjacent floating gates is increased, and the area of the floating gates between adjacent word lines is increased to shift the threshold voltage (Vt) due to the interference effect by the interference capacitor. (Shift) is caused, making normal cell operation difficult. In addition, since the topology is too high after the gate pattern is formed, the gate pattern may be leaned, thereby degrading device characteristics.

In order to reduce the interference effect, it is advantageous to reduce the thickness of the floating gate, but in this case, the interface area between the floating gate and the control gate is reduced, thereby reducing the coupling ratio. Measures are taken to overcome the existing monotonous floating gate by changing the shape of the existing monotonous floating gate, but it is difficult to secure the desired surface area of the floating gate by a simple method, and the problem of poly residue in the peripheral circuit area is high. Very difficult to control

According to the present invention, a floating gate having a lower width than an upper portion is formed, and the floating gate and the control gate are formed in a horizontal structure, thereby improving an interference effect between cells and a desired coupling ratio. The present invention provides a flash memory device and a method of manufacturing the same, which can secure a gate pattern from being leaked while being secured.

In a flash memory device according to an embodiment of the present invention, a stacked film of a tunnel insulating film, a first conductive film, and a sacrificial insulating film is formed in an active region of a semiconductor substrate, and a stacked film and a planarized device isolation film are formed in a device isolation region of a semiconductor substrate. do. The sacrificial insulating layer between the regions where the floating gate is to be formed is removed to protrude the device isolation layer. A spacer for exposing a part of the first conductive film is formed on the sidewall of the protruding element isolation film. A second conductive film filling the inside of the spacer is formed on the exposed first conductive film. A portion of the spacer and the insulating film are etched to expose the sidewall of the second conductive film and the upper sidewall of the first conductive film. Forming a dielectric film and a control gate along the surfaces of the remaining insulating film and the exposed first and second conductive films.

The second conductive layer is formed to have a narrower width than the first conductive layer, and the sacrificial insulating layer is formed of a material having a different etching selectivity from that of the device isolation layer.

The spacer is formed of an oxide film or a nitride film, and the oxide film is a high temperature thermal oxide film, a TEOS film, It is formed of any one of HLD films.

Before etching the spacers and the portions of the insulating layer, a portion of the second conductive layer is etched to form a recessed region exposing the upper sidewall of the spacer on the second conductive layer, and forming an etch stop layer in the recessed region. Include.

The present invention has the following effects.

First, by forming a floating gate having a lower width than the upper portion to reduce the area facing between adjacent floating gates, the program threshold voltage (Vt) shift between word lines by improving the interference effect between adjacent cells. Can be suppressed.

Second, by lowering the topology of the gate pattern by forming a structure between the floating gate and the control gate in a horizontal structure, it is possible to prevent the leaching of the gate pattern.

Third, by inserting a control gate between the floating gate to maintain or improve the coupling ratio (Coupling Ratio), it is possible to lower the operating voltage or maintain or improve the program / erase efficiency.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but should be understood by those of ordinary skill in the art. It is preferred that the present invention be interpreted as being provided to more fully explain the invention.

1A to 1F are layout views showing process steps in order to explain a method of manufacturing a flash memory device according to an embodiment of the present invention, and FIGS. 2A to 2F are lines A-A of FIGS. 1A to 1F. Process sectional drawing shown in order of process in order to demonstrate the manufacturing method of the state cut | disconnected to, and FIG. 3A-3F is process for demonstrating the manufacturing method of the state cut | disconnected by the line B-B of FIGS. 1A-1F. 4A to 4F are process cross-sectional views shown in order, and FIGS. 4A to 4F are process cross-sectional views shown in order of process to explain a manufacturing method cut along the line C-C 'of FIGS. 1A to 1F.

Referring to FIGS. 1A, 2A, 3A, and 4A, a laminated film of a tunnel insulating film 102, a first conductive film 104, and a sacrificial insulating film 106 patterned in the bit line direction is formed in an active region of a semiconductor substrate 101. The device isolation layer 110 is formed in the device isolation region of the semiconductor substrate 101. Hereinafter, an example of a process of forming the laminated film of the tunnel insulating film 102, the first conductive film 104, and the sacrificial insulating film 106 and the device isolation film 110 will be described in detail. First, a tunnel insulating film 102, a first conductive film 104, a sacrificial insulating film 106, and a hard mask film (not shown) are sequentially formed on the semiconductor substrate 101. The tunnel insulating layer 102 may be formed of a silicon oxide layer (SiO ₂ ), and in this case, may be formed by an oxidation process. The first conductive layer 104 is used as a floating gate of a flash memory device, and may be formed of a laminated film of a polysilicon layer, a metal layer, a polysilicon layer, and a metal layer. Preferably, the first conductive film 104 is formed of a polysilicon film, and is undoped in order to lower the doping concentration of impurities at the interface between the first conductive film 104 and the tunnel insulating film 102. It is more preferable to form with a polysilicon film. The sacrificial insulating layer 106 may be formed of a material having an etch selectivity different from that of the first conductive layer 104, and may be formed of a nitride film-based material such as silicon nitride (Si ₃ N ₄ ) or silicon oxynitride (SiON). The thickness of the sacrificial insulating layer 106 is formed in consideration of the height of the final floating gate. The hard mask layer may be used as an etching mask during subsequent trench formation, and may include oxide, SiON, amorphous carbon, or the like.

Next, the trench 108 is formed by etching the hard mask film, the sacrificial insulating film 106, the first conductive film 104, the tunnel insulating film 102, and the semiconductor substrate 101 in the device isolation region. More specifically described as follows. A photoresist (not shown) is applied on the hard mask film, followed by exposure and development to form a photoresist pattern (not shown) that exposes the hard mask film in the device isolation region. Subsequently, the hard mask film of the device isolation region is etched by an etching process using a photosensitive film pattern. Thereafter, the photoresist pattern is removed. Subsequently, the first conductive film 104 and the tunnel insulating film 102 are etched by an etching process using the hard mask film pattern as a mask. As a result, the semiconductor substrate 101 in the element isolation region is exposed. Subsequently, the semiconductor substrate 101 of the exposed device isolation region is etched to a predetermined depth. As a result, the trench 108 is formed in the device isolation region. As such, the trench 108 is preferably formed by performing a Self Align-Shallow Trench Isolation (SA-STI) process on the semiconductor substrate 101.

Subsequently, an insulating film (not shown) is deposited on the hard mask film pattern including the trench 108 so that the trench 108 is filled, and then the insulating film is flattened until the surface of the sacrificial insulating film 106 is exposed. ). The device isolation layer 110 may be formed of an oxide-based material, for example, a spin on glass (SOG) film, a boron-phosphosilicate glass (BPSG) film, a plasma enhanced tetra ethyl ortho silicate (peteos) film, or an undoped silicate (USG). It may be formed of any one selected from a glass film, a PSG (Phosphorus Silicate Glass) film, and an HDP (High Density Plasma) oxide film. The planarization process may be performed by a chemical mechanical polishing (CMP) process or an etch back process. As a result, an insulating film remains in the isolation region in which the trench 108 is formed, and thus the isolation layer 110 is formed. In addition, a laminated film of the tunnel insulating film 102, the first conductive film 104, and the sacrificial insulating film 106 is formed in the active region of the semiconductor substrate 101.

1B, 2B, 3B, and 4B, a first conductive film 104 is formed in an active region of a semiconductor substrate 101 on which a floating gate is to be formed, and the first conductive films 104 are formed in a bit line direction. A junction region 101a is formed in the lower semiconductor substrate 101, and a first insulating layer 112 is formed on the junction region 101a to fill the sacrificial insulating layer 106. Hereinafter, an example of the formation process of the 1st conductive film 104, the junction area | region 101a, and the 1st insulating film 112 is demonstrated in detail. First, a mask (not shown) is formed on the sacrificial insulating layer 106 and the device isolation layer 110 to expose the sacrificial insulating layer 106 corresponding to the regions where the floating gate is to be formed. The mask may be formed using a photoresist pattern, and may be formed by applying photoresist on the sacrificial insulating layer 106 and the device isolation layer 110 and patterning the photoresist with exposure and development. Subsequently, the sacrificial insulating layer 106, the first conductive layer 104, and the tunnel insulating layer 102 are sequentially etched between the regions where the floating gate is to be formed by an etching process using a mask. As a result, the semiconductor substrate 101 between the regions where the floating gate is to be formed is exposed. In the region where the floating gate is to be formed, a first conductive layer 104 patterned in a word line direction perpendicular to the isolation layer 110 and a bit line direction parallel to the isolation layer 110 is formed.

Subsequently, an ion implantation process is performed to form the junction regions 101a in which impurities are implanted in the exposed semiconductor substrate 101. The mask is then removed. In addition, an ion implantation process may be performed after removing a mask.

Subsequently, after the first insulating film is deposited on the junction region 101a, the sacrificial insulating film 106, and the device isolation layer 110, the first insulating film is planarized until the sacrificial insulating film 106 is exposed. The planarization process can be performed by a CMP process or an etch back process. As a result, a first insulating film 112 is formed on the junction region 101a to fill the gaps between the first conductive films 104 and the sacrificial insulating films 106. The first insulating layer 112 may be formed of a material having an etch selectivity different from that of the sacrificial insulating layer 106, and may be preferably formed of a thermal oxide layer.

Referring to FIGS. 1C, 2C, 3C, and 4C, a portion of the first conductive layer 104 is exposed along the sidewall of the isolation layer 110 and the sidewall of the first insulating layer 112 on the first conductive layer 104. The spacer 114 is formed, and a second conductive layer 116 is formed on the exposed first conductive layer 104 to fill the inside of the spacer 114. Hereinafter, an example of the formation process of the spacer 114 and the second conductive film 116 will be described in detail. First, the sacrificial insulating film 106 is removed. The sacrificial insulating film 106 is removed by a wet etching process, and preferably, a sacrificial insulating film using a wet dip-out process using a phosphoric acid solution (H ₃ PO ₄ ) having a high temperature of 120 to 150 ° C. Selectively removes 106 only. As a result, the surface of the first conductive film 104, the sidewalls of the device isolation layer 110 on the first conductive film 104, and the sidewalls of the first insulating film 112 are exposed.

Next, an insulating film (not shown) is deposited on the device isolation layer 110 including the exposed first conductive film 104 and the first insulating film 112. Thereafter, the insulating layer is etched by a spacer etching process to expose a portion of the first conductive layer 104 along the sidewall of the device isolation layer 110 and the sidewall of the first insulating layer 112 on the first conductive layer 104. Form 114. The spacer etching process may be performed by an etch back process. The spacer 114 may be formed of an oxide film or a nitride film. The oxide film may include a high temperature oxide (HTO) film, a tetra ethyl ortho silicate (TEOS) film, and the like. High Temperature Low Deposition (HLD) Film It may be formed of any one. In this case, the spacer 114 may be formed in a square ring shape.

1D, 2D, 3D, and 4D, a second conductive film 116 having a narrower width than the first conductive film 104 is formed on the first conductive film 104, and the second conductive film 116 is formed. The etch stop layer 120 is formed on the. In addition, sidewalls of the second conductive film 116 and the upper sidewalls of the first conductive film 104 between the first insulating film 112 are exposed. Hereinafter, an example of a process of forming the second conductive layer 116 and the etch stop layer 120 will be described in detail. First, a conductive film (not shown) is deposited on the first conductive film 104, the spacer 114, the first insulating film 112, and the device isolation film 110, and then the conductive film is planarized with an etch back. The etch back process is etched to expose the upper sidewall of the spacer 114 to form a recessed region (not shown) on the second conductive layer 116. As a result, a second conductive film 116 narrower than the first conductive film 104 is formed on the first conductive film 104. The second conductive layer 116 may be formed at the upper center of the first conductive layer 104. At this time, a floating gate 118 formed of a laminated film of the first conductive film 104 and the second conductive film 116 narrower than the first conductive film 104 is formed. As such, in the present invention, the floating gate 118 having a lower width than the upper portion may be formed to reduce the area facing between the adjacent floating gates 118. Accordingly, the interference effect between the adjacent cells can be improved to suppress the program threshold voltage Vt shift between the word lines.

Then, an insulating film is deposited on the second conductive film 116, the spacer 114, and the device isolation layer 110 to fill the recess region on the second conductive film 116. Subsequently, the insulating layer is flattened until the device isolation layer 110 is exposed to form an etch stop layer 120 in the recess region on the second conductive layer 116. The etch stop layer 120 may be formed of a nitride-based material, for example, silicon nitride layer (Si ₃ N ₄ ) or silicon oxynitride layer (SiON). The planarization process can be performed by a CMP process or an etch back process.

Meanwhile, the etch stop layer 120 may be omitted, and in this case, the second conductive layer 116 is formed to be planarized with the upper surface of the spacer 114.

Subsequently, the spacer 114 having the same width as that of the second conductive layer 116 may cross the first insulating layer 112 and the element isolation layer 110 on the etch stop layer 120, the device isolation layer 110, and the spacer 114. ) To form a mask (not shown). Then, the exposed spacer 114 and the exposed first insulating layer 112 are selectively etched by an etching process using a mask. In this case, all of the exposed spacers 114 are removed, and the spacers 114 remain on one side and the other side of the second conductive layer 116 between the device isolation layer 110 and the second conductive layer 116.

On the other hand, the first insulating film 112 is maintained at a predetermined thickness or more to stably control the high bias applied to the control gate and the semiconductor substrate 101 to be formed later. It is left to a thickness of 50-250 mm. As a result, the sidewalls of the second conductive layer 116 and the upper sidewalls of the first conductive layer 104 between the remaining first insulating layers 112 are exposed.

1E, 2E, 3E, and 4E, a dielectric film 122 is formed along the surfaces of the floating gate 118 and the first insulating layer 112, and the dielectric film 122 between the floating gates 118 is formed. The control gate 124 is formed on. Hereinafter, an example of a process of forming the dielectric film 122 and the control gate 124 will be described in detail. First, a dielectric layer 122 is formed on the floating gate 118, the first insulating layer 112, the etch stop layer 120, the device isolation layer 110, and the spacer 114. The dielectric film 122 may be formed of a stacked film of an oxide film, a nitride film, and an oxide film (Oxide-Nitride-Oxide (ONO)). Thereafter, the dielectric layer 122 is planarized to the point where the etch stop layer 120 is exposed. When the etch stop layer 120 is omitted, the etching stop layer 120 is planarized until the second conductive layer 116 is exposed. Planarization can be performed by a CMP process or an etch back process.

Subsequently, a mask (not shown) is formed on the device isolation layer 110 to expose a region where the word line is to be formed. Then, a portion of the device isolation layer 110 is etched by an etching process using a mask. The device isolation layer 110 may be left to have a thickness of 300 to 500 kW to stably control the high bias applied to the control gate to be formed later and the semiconductor substrate 101.

Subsequently, a control gate 124 is formed on the dielectric layer 122 between the floating gates 118 and the exposed device isolation layer 110. Hereinafter, the control gate 124 may be formed using any one of the following three manufacturing methods.

First, after the conductive film is formed on the dielectric film 122 to fill the spaces between the floating gates 118, the conductive film is planarized until the etch stop layer 120 is exposed. The conductive film may be formed of a polysilicon film or a metal layer. In this case, the metal layer may include a metal silicide layer, and may be preferably formed of tungsten (W) or tungsten silicide (WSi). The planarization process can be performed by a CMP process or an etch back process. When the etch stop layer 120 is omitted, the planarization process is performed until the device isolation layer 110 is exposed. As a result, a control gate 124 is formed between the floating gates 118.

Second, a polysilicon film (not shown) and a metal layer (not shown) are sequentially formed on the dielectric film 122 to fill the spaces between the floating gates 118. In this case, the metal layer may include a metal silicide layer, and may be preferably formed of tungsten (W) or tungsten silicide (WSi). Thereafter, the metal layer and the polysilicon layer are planarized until the etch stop layer 120 is exposed. The planarization process can be performed by a CMP process or an etch back process. When the etch stop layer 120 is omitted, the planarization process is performed until the device isolation layer 110 is exposed. As a result, a control gate 124 is formed between the floating gates 118 and formed of a laminated film of a polysilicon film and a metal layer.

Third, a polysilicon film (not shown) is formed on the dielectric film 122 to fill the spaces between the floating gates 118, and then an etch back process of the polysilicon film is performed until the etch stop layer 120 is exposed. A recess region (not shown) that exposes the upper sidewall of the dielectric film 122 is formed. When the etch stop layer 120 is omitted, the planarization process is performed until the device isolation layer 110 is exposed. Then, a metal layer (not shown) is formed on the polysilicon layer, the dielectric layer, the device isolation layer 110, and the etch stop layer 120 remaining to fill the recess region. In this case, the metal layer may include a metal silicide layer, and may be preferably formed of tungsten (W) or tungsten silicide (WSi). Thereafter, the metal layer is planarized until the etch stop layer 120 is exposed. The planarization process can be performed by a CMP process or an etch back process. When the etch stop layer 120 is omitted, the planarization process is performed until the device isolation layer 110 is exposed. As a result, a control gate 124 is formed between the floating gates 118 and formed of a laminated film of a polysilicon film and a metal layer.

As described above, the control gate 124 may be formed of a single layer of a polysilicon film or a metal layer, or may be formed of a laminated film of a polysilicon film and a metal layer. The control gates 124 formed on different strings are connected to each other to form word lines (not shown). Under the control gate 124, the total thickness of the thickness of the first insulating film 112 and the thickness of the dielectric film 122 is 300 in order to stably control the high bias applied to the control gate 124 and the semiconductor substrate 101. To 500 kPa.

At this time, a gate pattern (not shown) including the tunnel insulating film 102, the floating gate 118, the dielectric film 122, and the control gate 124 is formed.

The conventional gate pattern is formed of a vertical gate in which a tunnel insulating film, a floating gate, a dielectric film, and a control gate are formed in a stack structure. However, in the present invention, since the control gate 124 is inserted between the floating gates 118, the control gate 124 is formed in a horizontal structure between the floating gate 118 and the control gate 124. As a result, the topology of the gate pattern may be lowered, thereby preventing the gate pattern from being tilted.

In addition, the control gate 124 may be inserted between the floating gates 118 to maintain or improve a coupling ratio, thereby lowering an operating voltage or maintaining or improving a program / erase efficiency.

1F, 2F, 3F, and 4F, the second insulating layer 126 is disposed on the control gate 124, the device isolation layer 110, the spacer 114, the dielectric layer 122, and the etch stop layer 120. To complete the gate forming process. The second insulating film 126 may be used as an interlayer insulating film as long as it is an oxide film-based material.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A through 1F are layout views illustrating a process order to explain a method of manufacturing a flash memory device according to an exemplary embodiment.

2A to 2F are cross-sectional views showing process steps in order to explain a manufacturing method cut along the line A-A 'of FIGS. 1A to 1F.

3A to 3F are cross-sectional views showing process steps in order to explain the manufacturing method of the state taken along the line BB ′ of FIGS. 1A to 1F.

4A to 4F are cross-sectional views showing process steps in order to explain a manufacturing method cut along the line C-C 'of FIGS. 1A to 1F.

<Description of the symbols for the main parts of the drawings>

101: semiconductor substrate 101a: junction region

102 tunnel insulating film 104 first conductive film

106: sacrificial insulating film 108: trench

110 device isolation layer 112 first insulating film

114 spacer 116 second conductive film

118: floating gate 120: etching stop film

122: floating gate 124: control gate

Claims (6)

Forming a stacked film of a tunnel insulating film, a first conductive film, and a sacrificial insulating film in an active region of the semiconductor substrate, and forming the stacked film and the planarized device isolation film in the device isolation region of the semiconductor substrate; Removing the sacrificial insulating layer between the regions where the floating gate is to be formed to protrude the device isolation layer; Forming a spacer on a sidewall of the protruding element isolation layer to expose a portion of the first conductive layer; Forming a second conductive film filling the inside of the spacer on the exposed first conductive film; Etching portions of the spacer and the insulating layer to expose sidewalls of the second conductive layer and upper sidewalls of the first conductive layer; And Forming a dielectric film and a control gate along the surfaces of the remaining insulating film and the exposed first and second conductive films. The method of claim 1, And the second conductive film is formed to have a narrower width than the first conductive film. The method of claim 1, The sacrificial insulating layer may be formed of a material having a different etching selectivity from the isolation layer. The method of claim 1, And the spacer is formed of an oxide film or a nitride film. The method of claim 4, wherein The oxide film is a high temperature thermal oxide film, TEOS film and A method of manufacturing a flash memory device formed of any one of HLD films. The method of claim 1, wherein before etching a portion of the spacer and the insulating layer, Etching a portion of the second conductive layer to form a recess region on the second conductive layer to expose the upper sidewall of the spacer; And And forming an etch stop layer in the recess region.

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