KR101034940B1 - Method of manufacturing a non-volatile memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a nonvolatile memory device, and in particular, providing a semiconductor substrate including an element isolation layer having a lower height than the electron storage layer between the electron storage layer and the electron storage layer, Forming a spacer on sidewalls of the electron storage layer, etching the device isolation layer exposed between the spacers to form a groove in the center of the device isolation layer, performing the spacer removing process, and forming the groove Forming a dielectric film on the dielectric film and forming a conductive film on the dielectric film to fill the space between the groove and the electron storage film, thereby forming an insulating film having an etching selectivity much higher than that of the oxide film. After that, a groove is formed in the center of the device isolation layer by using a spacer etched from the insulating layer. As according to improve cycling (Cycling) characteristic, and it is possible to reduce the effect of interference (Interference Effect) between cells and, increasing the stability, reproducibility, and the margin of the process.

Device Isolation, Spacers, Etch Selectivity, Cycling, Cell Interference

Description

Method of manufacturing a non-volatile memory device

1A to 1H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 102 tunnel insulating film

104: electron storage film 104a: floating gate

106: buffer oxide film 108: nitride film

110: hard mask 112: device isolation mask

114: trench 116: device isolation film

118: insulating film 118a: spacer

120 dielectric film 122 control gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory device. In particular, a nonvolatile memory device having a groove formed in the center of an isolation layer by an etching process using a spacer after forming a spacer with an insulating film having an etching selectivity much higher than an oxide film. It relates to a method for producing.

In general, a nonvolatile memory device programs or erases data of electrons of a floating gate electrode through F-N tunneling to record information. As such, in order to store information, nonvolatile memory devices require floating gate electrodes that are isolated from each device. In order to form a conventional isolated floating gate electrode, a first polysilicon film is formed through a device isolation process of self-aligned shallow trench isolation (SA-STI), and a second polysilicon film is formed on the second polysilicon film. The silicon film was patterned to form a floating gate electrode pattern. In this case, the second polysilicon film should be formed thick due to the problem of coupling ratio of the cell, and the first polysilicon film should be formed thin due to the problem of device isolation process. As the size of the cell gradually decreases, the area to be etched to isolate the floating gate electrode pattern is reduced, and the step to be etched increases. As a result, polysilicon remains during the etching process to isolate the floating gate electrode, which adversely affects the operation of the device. In order to solve this problem, it is advantageous to reduce the thickness of the second polysilicon film, but it is also difficult due to the problem of the coupling ratio of the cell described above.

In order to solve the above problem, an ASA-STI (Advanced Self-Aligned Shallow Trench Isolation) process that implements the floating gate and the device isolation region at once is used. This process solves the overlap problem between the floating gate and the device isolation region, but the surface area of the floating gate is limited because the size of the polysilicon film of the floating gate is determined by the device isolation region. As a result, the coupling ratio of the cell is reduced, and due to the deterioration of cycling characteristics, the device isolation layer between the floating gates is removed, thereby limiting the effective field oxide height (EFH). On the other hand, in order to improve the cycling characteristics, the higher the EFH, the more advantageous, in which case there is a problem that the interference characteristics with the adjacent polysilicon film is reduced.

The present invention improves the cycling characteristics by forming a groove in the center of the device isolation layer by forming a spacer with an insulating film having an etching selectivity higher than that of the oxide film and then using a spacer, thereby improving the cycling characteristics and inter-cell interference effects (interference) It is to provide a method of manufacturing a nonvolatile memory device that can reduce the effect) and increase the stability, reproducibility and margin of the process.

According to an aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, including: providing a semiconductor substrate including an element isolation layer having a height lower than that of the electron storage layer between the electron storage layer and the electron storage layer; Forming a spacer on the sidewalls of the electron storage layer on the separator, forming a groove in the center of the device isolation layer by etching the device isolation layer exposed between the spacers, performing a spacer removing process, and forming a groove on the device isolation layer Forming a dielectric film, and forming a conductive film on the dielectric film so that the space between the groove and the electron storage film is filled.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the embodiments of the present invention can be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, and those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

1A to 1H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a tunnel insulating layer 102, a floating gate electron storage layer 104, and a device isolation mask 112 are sequentially formed on a semiconductor substrate 100. The device isolation mask 112 may be formed as a stacked structure of the buffer oxide layer 106, the nitride layer 108, and the hard mask 110. The hard mask 110 may be formed of nitride, oxide, SiON or amorphous carbon. On the other hand, the electron storage layer 104 is for forming a floating gate of the nonvolatile memory device, it is formed of a polysilicon film.

Referring to FIG. 1B, the device isolation mask 112, the electron storage layer 104, and the tunnel insulating layer 102 of the device isolation region are sequentially etched to expose the device isolation region of the semiconductor substrate 100. More specifically described as follows. A photoresist (not shown) is applied on the device isolation mask 112 and an exposure and development process is performed to form a photoresist pattern (not shown) that exposes the device isolation mask 112 in the device isolation region. Subsequently, the device isolation region of the device isolation mask 112 is etched by an etching process using a photoresist pattern. Thereafter, the photoresist pattern is removed. Subsequently, the electron storage film 104 and the tunnel insulating film 102 are etched by an etching process using the device isolation mask 112. As a result, the semiconductor substrate 100 in the device isolation region is exposed. In the process of etching the nitride film 108, the buffer oxide film 106, the electron storage film 104, and the tunnel insulating film 102, the hard mask 110 is also etched by a predetermined thickness. Subsequently, the semiconductor substrate 100 of the exposed device isolation region is etched by an etching process to form the trench 114.

Referring to FIG. 1C, an insulating material is deposited to fill the trench 114 to form an insulating film (not shown). The insulating film may be formed of an oxide film, and preferably, an HDP (High Density Plasma) oxide film, a spin on glass (SOG) film, a boron phosphorus silicate glass (BPSG) film, a phosphorous Silicate glass (PSG) film, and an undoped silicate galss (USG) It may be formed of any one selected from among the film. Thereafter, the insulating film is planarized to a point where the surface of the nitride film 108 of the device isolation mask 112 is exposed by a chemical mechanical polishing (CMP) process, thereby forming a device isolation film (not shown). Thereafter, the device isolation layer is recessed to expose a portion of the outer wall of the electron storage layer 104 to form the device isolation layer 116 in which the effective field oxide height (EFH) is controlled. In this case, the device isolation layer 116 is formed lower than the height of the electron storage layer 104 and higher than the height of the active region of the semiconductor substrate 100. Thereafter, the remaining nitride film 108 is removed.

Meanwhile, an oxidation process may be further performed to etch damage caused on the sidewalls and the bottom of the trench 114 by an etching process for forming the trench 114 before forming the device isolation layer 116. As a result, the sidewalls and the bottom surface of the trench 114 are oxidized through an oxidation process to form an etch damage layer as a sidewall oxide layer (not shown).

Referring to FIG. 1D, an insulating film 118 is formed along the surfaces of the electron storage film 104 and the device isolation film 116. The insulating film 118 is formed to form a spacer (not shown) to be formed later, and has a thickness of 100 kV to 1000 kV.

Here, the insulating film 118 is formed of a SiON film using SiH ₄ , NH _3, and N ₂ O gases to have a higher etching selectivity than the oxide film of the device isolation layer 116 in a subsequent spacer etching process. Thus, the SiON film formed using the SiH ₄ , NH ₃ and N ₂ 0 gas has very different physical properties from the SiON film formed using the existing SiH ₄ , N ₂ 0 and He gases. That is, when NH ₃ is used to deposit the SiON film, the etching selectivity may be about 30 times faster than the HDP oxide film.

Referring to FIG. 1E, the spacer 118a is formed on the sidewall of the insulating layer 118 through which the electron storage layer 104 is exposed by using a spacer etching process. The spacer etching process is performed by a dry etching process, and in order to minimize the loss of the device isolation layer 116, an etching gas having an etching selectivity higher than that of the device isolation layer 116 may be used. Preferably, the spacer etching process is performed using an etching gas of CH ₂ F ₂ or CF ₄ series, and the etching target thickness is 100 kPa to 1000 kPa.

When the spacer etching process is performed, the insulating film 118 deposited on the horizontal portion is completely removed and only the insulating film 118 deposited on the vertical portion thicker than the horizontal portion remains, whereby the spacer 118a is formed only on the sidewall of the electron storage layer 104. ) Is formed. Thus, the SiON film of the insulating film 118 is easily etched to form the spacer 118a while minimizing the loss of the device isolation film 116 to minimize the difference in the etching amount of the device isolation film 116 according to the process variation. Stability, reproducibility and margins can be increased.

Referring to FIG. 1F, the device isolation layer 116 between the spacers 118a is etched to form the grooves A. Referring to FIG. The etching process for forming the grooves A is performed by a dry etching process, using an etching gas having an etching selectivity higher than that of the spacer 118a with respect to the device isolation layer 116 to minimize the loss of the spacer 118a. do. Preferably, the etching process is carried out using an etching gas of the C ₄ F ₆ , C ₄ F ₈ or C ₅ F ₈ series. The etching process is performed using an etching target thickness of 100 kPa to 1000 kPa, wherein the groove A is formed higher than the height of the active region of the semiconductor substrate 100.

In this way, the device isolation layer 116 can be easily etched to form a groove A in the center of the device isolation layer 116 while minimizing the loss of the spacer 118a to minimize the topology variation due to the process variation. . In addition, it is possible to increase the stability, reproducibility and margin of the process for controlling the effective field oxide height (EFH).

Referring to FIG. 1G, a spacer 118a is removed. The spacer 118a may be removed by a wet etching process, and may be preferably performed using an HF solution, a buffered oxide etchant (BOE), or a standard cleaning-1 (SC-1) solution.

The spacer 118a made of a SiON film formed by using SiH ₄ , NH _3, and N ₂ 0 gases according to the present invention uses a minimum etching time because the etching rate by the etchant is fast as described above. It can be removed. Therefore, the spacer removal process is performed for 1 to 100 seconds using HF solution, BOE or SC-1 solution.

Meanwhile, in the process of removing the spacer 118a, the device isolation layer 116 between the spacers 118a may also be etched by a predetermined thickness so that the depth of the groove A may be lowered. However, since the process time for removing the spacer 118a is shortened, the loss of the device isolation layer 116 can be minimized to control the effective oxide height EFH, so that the control gate and the active region of the semiconductor substrate 100 are subsequently formed. By controlling the minimum distance from the top, the cycling characteristics can be improved. In addition, the process time can be shortened.

Referring to FIG. 1H, the dielectric film 120 and the control gate conductive film (not shown) are formed on the electron storage film 104 including the device isolation film 116 having the groove A formed therein. The dielectric body film 120 may be formed in an oxide-nitride-oxide (ONO) stacked structure. The conductive film may be formed of a polysilicon film, a metal film or a laminated film thereof, and preferably, a polysilicon film.

 Thereafter, the conductive film, the dielectric film 120, and the electron storage film 104 are sequentially patterned in a conventional process. As a result, the floating gate 104a formed of the electron storage film 104 and the control gate 122 made of the conductive film are formed.

The present invention improves the cycling characteristics by widening the minimum distance between the upper portion of the active region of the semiconductor substrate 100 and the control gate when forming the control gate through the profile forming the groove A in the center of the device isolation layer 116. In addition, the inter-cell interference effect can be reduced by forming the control gate deeply between the floating gates.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

As described above, the present invention has the following effects.

First, the spacer insulating film is formed of a SiON film having a much higher etch selectivity than the oxide film using SiH ₄ , NH ₃ and N ₂ O gases, and thus the ratio of the spacer selectivity and the etch selectivity during the etching of the center portion of the device isolation layer using the spacer. The loss of the etched film can be minimized and process stability, reproducibility and margins can be increased.

Second, by forming a profile to etch the central portion of the device isolation layer between the floating gates to improve the cycling characteristics by increasing the minimum distance between the active region of the semiconductor substrate and the control gate, so that the control gate is formed deep in the position between the floating gates As a result, the cell interference effect can be reduced.

Third, the process time can be shortened when removing the spacer formed of the SiON film having a much higher etching selectivity than the oxide film.

Claims (12)

Providing a semiconductor substrate between an electron storage layer and the electron storage layer, the semiconductor substrate including a device isolation layer having a lower height than the electron storage layer; Forming a spacer on a sidewall of the electron storage layer on the device isolation layer; Etching the device isolation layer exposed between the spacers to form a groove in the center of the device isolation layer; Performing the spacer removal process; Forming a dielectric film on the device isolation film in which the groove is formed; And And forming a conductive film on the dielectric film to fill the space between the groove and the electron storage film. The method of claim 1, And forming the device isolation layer higher than an active region height of the semiconductor substrate. The method of claim 1, wherein the forming of the spacers comprises: Forming an insulating film along surfaces of the electron storage film and the device isolation film; And A method of manufacturing a nonvolatile memory device comprising performing a spacer etching process on the insulating film. The method of claim 1, The spacer is formed of a SiON film formed using SiH ₄ , NH ₃ and N ₂ O gas. The method of claim 3, wherein The insulating film is a method of manufacturing a nonvolatile memory device to a thickness of 100 ~ 1000Å. The method of claim 3, wherein The spacer etching process is a method of manufacturing a nonvolatile memory device by dry etching using an etching gas of the CH ₂ F ₂ or CF ₄ series. The method of claim 3, wherein The spacer etching process is a method of manufacturing a nonvolatile memory device to perform the etching target thickness of 100 ~ 1000Å. The method of claim 1, The groove of the device isolation layer is formed higher than the height of the active region of the semiconductor substrate. The method of claim 1, The forming of the grooves may be performed by dry etching using an etching gas of C ₄ F ₆ , C ₄ F _8, or C ₅ F ₈ series. The method of claim 1, The method of claim 1, wherein the forming of the groove is performed using an etching target thickness of 100 μs to 1000 μm. The method of claim 1, The spacer removing process is performed using a HF solution, a BOE or SC-1 solution. The method of claim 11, The spacer removing process is performed for 1 to 100 seconds.

Images