KR100336568B1 - Device Separating Method of Semiconductor Device - Google Patents
Device Separating Method of Semiconductor Device Download PDFInfo
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- KR100336568B1 KR100336568B1 KR1019980024224A KR19980024224A KR100336568B1 KR 100336568 B1 KR100336568 B1 KR 100336568B1 KR 1019980024224 A KR1019980024224 A KR 1019980024224A KR 19980024224 A KR19980024224 A KR 19980024224A KR 100336568 B1 KR100336568 B1 KR 100336568B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 230000003064 anti-oxidating effect Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000006731 degradation reaction Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 10
- 230000006866 deterioration Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 활성영역의 열화를 방지할 수 있는 반도체 소자의 소자 분리막 형성방법을 개시한다. 개시된 본 발명의 소자 분리막 형성방법은, 상부면에 질화막이 소정 두께로 전면 증착된 반도체 기판을 제공하는 단계: 상기 질화막 상에 상기 반도체 기판의 비활성영역들 상부 부분을 노출시키는 감광막 패턴을 형성하는 단계: 상기 노출된 질화막 부분들과 그 하부의 비활성영역들의 소정 두께를 선택적으로 식각하여 소정 폭 및 높이를 갖는 기둥 형태의 활성영역들을 형성하는 단계; 상기 식각 마스크로 사용된 감광막 패턴을 제거한 후에, 반도체 기판의 전면 상에 제1평탄화막을 두껍게 도포하는 단계; 상기 잔류되어 있는 질화막과 활성영역들의 상단부가 노출되도록 1차 식각 공정을 통해 상기 제1평탄화막의 소정 두께를 제거하는 단계; 상기 노출된 질화막 및 활성영역의 상단부 측면에 질화막 스페이서를 형성하는 단계: 상기 비활성영역에 잔류되어 있는 제1평탄화막을 2차 식각 공정을 통해 제거하는 단계; 열산화 공정을 실시하여 상기 활성영역의 상단부와 하단부 사이에 그들간을 전기적으로 분리시키는 산화막을 형성하는 단계; 상기 질화막 및 질화막 스페이서를 제거하는 단계: 전체 상부에 제2평탄화막을 도포하는 단계; 및 상기 활성영역의 상단부가 노출될 때까지 상기 제2평탄화막을 전면식각하여 상기 활성영역들간을 분리시키는 소자 분리막을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a device isolation film forming method of a semiconductor device capable of preventing degradation of an active region. According to an aspect of the present invention, there is provided a method of forming a device isolation layer, the method comprising: providing a semiconductor substrate on which a nitride film is entirely deposited to a predetermined thickness: forming a photoresist pattern on the nitride film exposing upper portions of inactive regions of the semiconductor substrate; Selectively etching a predetermined thickness of the exposed portions of the nitride layer and the non-active regions below the forming of the pillar-shaped active regions having a predetermined width and height; After removing the photoresist pattern used as the etching mask, thickly applying a first planarization film on the entire surface of the semiconductor substrate; Removing a predetermined thickness of the first planarization layer through a first etching process to expose the remaining nitride layer and upper ends of the active regions; Forming a nitride spacer on the exposed side of the nitride layer and the upper portion of the active region: removing the first planarization layer remaining in the inactive region through a secondary etching process; Performing a thermal oxidation process to form an oxide film electrically separating them between an upper end and a lower end of the active region; Removing the nitride layer and the nitride spacer: applying a second planarization layer on the entire upper portion; And forming a device isolation layer that separates the active regions by etching the entire surface of the second planarization layer until the upper end of the active region is exposed.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는, 활성영역의 열화를 방지할 수 있는 반도체 소자의 소자 분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device capable of preventing degradation of an active region.
현재, 반도체 소자의 제조 공정에서 소자들간을 전기적으로 분리시키기 위한 기술로는 LOCOS(LOCOS:local oxidation of silicon), 딥 트랜치(Deep Trench), 또는, 샐로우 트랜치(Shallow Trench) 등의 기술이 실시되고 있다.At present, a technique for electrically separating devices in a semiconductor device manufacturing process is implemented by techniques such as local oxidation of silicon (LOCOS), deep trench, or shallow trench. It is becoming.
그러나, 상기와 같은 기술들을 이용하여 소자 분리막을 형성하는 경우에는, 열산화막의 형성시에 반도체 기판의 활성영역에 인가되는 스트레스(Stress)에 의해 활성영역의 물성 및 전기적 특성이 열화됨은 물론 비활성영역의 분리가 완벽하게 이루어지지 않기 때문에, 활성영역들간의 누설 전류, 웰(Well)쪽으로의 누설전류, 또는 래치-업(Latch-Up) 등의 문제가 상존하였다.However, in the case of forming the device isolation layer using the above techniques, the physical and electrical properties of the active region are deteriorated by the stress applied to the active region of the semiconductor substrate when the thermal oxide film is formed, as well as the inactive region. Since the separation of the components is not completely performed, problems such as leakage current between the active regions, leakage current toward the well, or latch-up exist.
특히, 로코스 기술로 소자 분리막을 형성하는 경우에는 열산화 공정시에 발생되는 버즈-빅(bird's-beak)에 의해 활성영역이 잠식되는 문제가 발생되며, 이러한 문제를 해결하기 위하여 실시되고 있는 변형된 로코스 기술들에서는 버즈-빅에 의한 활성영역의 감소는 방지할 수 있으나, 오히려, 스트레스에 의한 활성영역의 물성 및 전기적 특성이 저하되는 문제점이 있었다.In particular, in the case of forming the device isolation layer using the LOCOS technology, a problem occurs in that the active region is encroached by bird's-beak generated during the thermal oxidation process. In the old Locos technologies, the reduction of the active area due to buzz-big can be prevented, but rather, the physical properties and electrical properties of the active area due to stress are deteriorated.
한편, 트랜치 기술을 이용한 소자 분리막 형성 방법은 로코스 기술을 이용할 경우에 발생되는 문제들이 상존함은 물론 공정이 복잡하다는 단점도 있다.On the other hand, the method of forming a device isolation layer using the trench technology has the disadvantage that the problems that occur when using the LOCOS technology and the process is complicated.
따라서, 활성영역에 인가되는 스트레스 또는 활성영역의 잠식과 같은 상기의 문제들을 해결하기 위하여 SOI (Silicon-On-Insulator) 기술이 고안되었다.Accordingly, the SOI (Silicon-On-Insulator) technology has been devised to solve the above problems such as stress applied to the active region or erosion of the active region.
상기한 SOI 기술은 반도체 기판 상에 절연층이 구비되고, 이 절연층의 상부에는 소자가 형성될 수 있는 활성영역이 구비된 기판 구조를 이용하는 기술로서, 이러한 SOI 기술은 고집적화에 유리하고, 특히, SOI 구조를 갖는 반도체 기판에 소자 분리막을 형성할 경우에는 활성영역에 대한 특성 저하없이 소자들간을 안정적으로 분리시킬 수 있다.The SOI technology described above uses a substrate structure having an insulating layer formed on a semiconductor substrate and having an active region in which an element can be formed. The SOI technology is advantageous for high integration, in particular, When the device isolation layer is formed on a semiconductor substrate having an SOI structure, the devices may be stably separated from each other without deteriorating characteristics of the active region.
그러나, 상기한 바와 같은 SOI 기술에서는 절연층이 개재된 3층 구조의 기판을 얻기 위해서는 두 개의 웨이퍼를 접합하거나, 또는, 반도체 기판에 산소 이온주입 및 어닐링 공정을 실시해야 하는데, 전자의 경우에는 SOI 기판이 고가이기 때문에 비용 측면에서 적용이 곤란한 문제점이 있으며, 후자의 경우에는 산소 이온 주입시에 발생되는 활성영역에서의 격자 결함이 후속의 어닐링 동안에 완전히 회복되지 못함으로써, 양질의 활성영역을 얻을 수 없다는 문제점이 있었다.However, in the SOI technology described above, in order to obtain a three-layer substrate having an insulating layer, two wafers are bonded or oxygen ion implantation and annealing processes are performed on a semiconductor substrate. Since the substrate is expensive, it is difficult to apply in terms of cost. In the latter case, lattice defects in the active region generated at the time of oxygen ion implantation cannot be completely recovered during subsequent annealing, thereby obtaining a high quality active region. There was no problem.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, SOI 기판을 사용하지 않고도, 손쉽게 SOI 구조를 갖는 기판을 형성함으로써, 활성영역에 인가되는 스트레스 및 상기 활성영역이 잠식되는 현상을 방지할 수 있는 반도체 소자의 소자 분리막 형성방법을 제공하는데, 그 목적이 있다.Therefore, the present invention devised to solve the above problems, by forming a substrate having an SOI structure easily, without using the SOI substrate, it is possible to prevent the stress applied to the active region and the phenomenon that the active region is eroded. It is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 소자 분리막 형성방법을 설명하기 위한 일련의 공정 단면도.1A to 1F are a series of cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 반도체 기판 11a : 활성영역11 semiconductor substrate 11a active region
12 : 질화막 13 : 감광막 패턴12: nitride film 13: photosensitive film pattern
14 : 제1평탄화막 15 : 질화막 스페이서14 first planarization film 15 nitride film spacer
16 : 산화막 17 : 제2평탄화막16: oxide film 17 second planarization film
20 : 소자 분리막20 device isolation film
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 소자 분리막 형성방법은, 활성영역들과 상기 활성영역들 사이에 비활성영역이 정의된 반도체기판을 제공하는 단계; 반도체기판 상에 질화막을 형성하는 단계; 질화막 상에 반도체 기판의 비활성영역들을 노출시키는 감광막 패턴을 형성하는 단계; 감광막 패턴을 마스크로 질화막 및 반도체기판의 비활성영역들의 소정두께로 식각하여 높이/폭 비가 2 이상이 되는 기둥 형태의 활성영역들을 형성하는 단계; 감광막 패턴을 제거하는 단계와, 반도체 기판 전면에 제1평탄화막을 형성하는 단계; 잔류되어 있는 질화막과 활성영역들의 상단부가 노출되며, 활서영역들 높이에 대하여 1/3 내지 2/3 정도가 잔류되도록 제 1평탄화막을 제거하는 단계; 잔류된 질화막 및 활성영역들의 상단부 측면에 질화막 스페이서를 형성하는 단계: 제1평탄화막을 제거하는 단계: 잔류된 질화막 및 질화막 스페이서를 산화방지용마스크로 반도체기판에 열산화 공정을 실시하되, 열산화 두께가 질화막 스페이서 하부에 미치지 못하게 하는 범위 내에서 진행되도록 하여, 활성영역의 상단부와 하단부 사이에 그들간을 전기적으로 분리시키는 산화막을 형성하는 단계; 잔류된 질화막 및 질화막 스페이서를 제거하는 단계: 반도체기판 전체에 제2평탄화막을 형성하는 단계; 및 활성영역들의 상단부가 노출될 때까지 제2평탄화막을 식각하여 활성영역들간을 분리시키는 소자 분리막을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a device isolation layer of a semiconductor device of the present invention includes providing a semiconductor substrate having active regions and an inactive region defined between the active regions; Forming a nitride film on the semiconductor substrate; Forming a photoresist pattern on the nitride film to expose inactive regions of the semiconductor substrate; Forming a pillar-shaped active region having a height / width ratio of two or more by etching the photoresist pattern with a mask to a predetermined thickness of the inactive regions of the nitride film and the semiconductor substrate; Removing the photoresist pattern, and forming a first planarization film on the entire surface of the semiconductor substrate; Removing the first planarization film so that the remaining nitride film and the upper end of the active regions are exposed and 1/3 to 2/3 of the active regions remain. Forming a nitride spacer on the upper side of the remaining nitride film and the active regions: removing the first planarization film: thermally oxidizing the remaining nitride film and nitride spacer on the semiconductor substrate with an anti-oxidation mask, Forming an oxide film to electrically proceed between the upper end and the lower end of the active region so as not to reach the lower portion of the nitride film spacer; Removing the remaining nitride film and nitride spacer: forming a second planarization film over the entire semiconductor substrate; And forming an isolation layer to etch the second planarization layer until the upper ends of the active regions are exposed to separate the active regions.
본 발명에 따르면, SOI 기술을 응용하여 소자 분리막을 형성하기 때문에 활성영역의 특성 저하를 방지할 수 있다.According to the present invention, since the device isolation layer is formed by applying the SOI technology, it is possible to prevent deterioration of the characteristics of the active region.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 소자 분리막 형성방법을 설명하기 위한 일련의 공정 단면도이다.1A through 1F are a series of cross-sectional views illustrating a method of forming a device isolation film according to an exemplary embodiment of the present invention.
우선, 도 1a에 도시된 바와 같이, 반도체 기판(11) 상에 질화막(12)을 1,000 내지 4,000Å 두께로 증착하고, 이 상부에 공지된 방법으로 반도체 기판의 비활성 영역들 상부의 질화막 부분들을 노출시키는 감광막 패턴(13)을 형성한다. 그런 다음, 상기 감광막 패턴(13)을 식각 마스크로 하는 식각 공정을 통해 노출된 질화막 부분들 및 반도체 기판의 비활성 영역들을 선택적으로 식각하여 기둥 형태의 활성영역들(11a)을 형성한다. 이때, 활성영역의 높이/폭의 비는 2이상이 되도록 한다.First, as shown in FIG. 1A, a nitride film 12 is deposited on the semiconductor substrate 11 to a thickness of 1,000 to 4,000 Å, and the nitride film portions on the inactive regions of the semiconductor substrate are exposed by a known method thereon. The photosensitive film pattern 13 to be formed is formed. Thereafter, the nitride layer portions exposed through the etching process using the photoresist pattern 13 as an etching mask and the inactive regions of the semiconductor substrate are selectively etched to form pillar-shaped active regions 11a. At this time, the ratio of the height / width of the active area is to be 2 or more.
다음으로, 도 1b에 도시된 바와 같이, 식각 마스크로 사용된 감광막 패턴을 제거한 상태에서, 전체 상부에 통상의 반도체 소자 제조 공정에서 평탄화막으로 이용되는 SOG막, BPSG막, 또는, PSG막 중에서 선택되는 하나의 막으로된 제1평탄화막(14)을 두껍게 도포하여 표면 평탄화를 달성하고, 이어서, HF 용액, 또는, 버퍼드(Buffered) HF 용액을 이용한 습식 식각이나, 혹은, 플라즈마를 이용한 등방성 건식식각 등의 공정을 실시하여 상기 제1평탄화막(14)의 일부를 제거한다.Next, as shown in FIG. 1B, in a state where the photoresist pattern used as an etching mask is removed, an SOG film, a BPSG film, or a PSG film, which is used as a planarization film in a normal semiconductor device manufacturing process, is selected on the entire upper portion. The first planarization film 14 made of one film is thickly applied to achieve surface planarization, and then wet etching using an HF solution or a buffered HF solution, or an isotropic dry method using a plasma. A part of the first planarization layer 14 is removed by performing a process such as etching.
이때, 잔류된 제1평탄화막(14)의 두께는 기둥 형태로된 활성영역(11a)의 높이에 대해 1/3 내지 2/3가 되도록 만든다.At this time, the thickness of the remaining first flattening film 14 is made to be 1/3 to 2/3 of the height of the active region 11a in the form of a column.
그런 다음, 도 1c에 도시된 바와 같이, 전체 상부에 재차 질화막을 소정 두께로 증착한 후, 상기 질화막에 대한 플라즈마 식각 공정을 실시하여 활성영역(11a)의 상단부에 질화막 스페이서(15)를 형성한다.Then, as illustrated in FIG. 1C, the nitride film is deposited on the entire upper portion again, and then the nitride film spacer 15 is formed on the upper end of the active region 11a by performing a plasma etching process on the nitride film. .
다음으로, 도 1d에 도시된 바와 같이, 앞서의 공정과 마찬가지로 HF 용액, 또는, 버퍼드 HF 용액을 이용한 습식 식각이나, 혹은, 플라즈마를 이용한 등방성 건식식각 공정으로 활성영역들(11a) 사이의 비활성영역에 잔류되어 있는 제1평탄화막을 제거한 후에, 열산화 공정을 실시한다.Next, as shown in FIG. 1D, the inertity between the active regions 11a may be a wet etching process using an HF solution, a buffered HF solution, or an isotropic dry etching process using a plasma as in the above process. After removing the first planarization film remaining in the region, a thermal oxidation step is performed.
이때, 활성영역(11a)의 상단부는 질화막(12) 및 질화막 스페이서(15)에 둘러쌓여 있기 때문에 열산화 반응이 일어나지 않는 반면에, 활성영역(11a)의 하단부는 노출되어 있기 때문에 측면으로 열산화 반응이 일어나게 된다.At this time, since the upper end portion of the active region 11a is surrounded by the nitride film 12 and the nitride spacer 15, no thermal oxidation reaction occurs, while the lower end portion of the active region 11a is exposed to thermally oxidize to the side surface. The reaction will take place.
이에 따라, 활성영역(11a)의 하단부에는 산화막(16)이 형성되며, 이러한 산화막(16)에 의해 활성영역(11a)의 상단부와 하단부는 전기적으로 분리되어 SOI 구조가 형성된다.Accordingly, an oxide film 16 is formed at the lower end of the active region 11a, and the upper and lower ends of the active region 11a are electrically separated by the oxide film 16 to form an SOI structure.
계속해서, 도 1e에 도시된 바와 같이, 활성영역(11a)의 상단부를 둘러쌓고 있는 질화막 및 질화막 스페이서를 인산 용액을 이용하여 제거하고, 이어서, 전체 상부에 앞서와 마찬가지로 SOG막 BPSG막 또는 PSG막 중에서 선택되는 하나의 막으된 제2평탄화막(17)을 두껍게 도포한다.Subsequently, as illustrated in FIG. 1E, the nitride film and the nitride film spacer surrounding the upper end of the active region 11a are removed using a phosphoric acid solution, and then the SOG film BPSG film or PSG film as before the entire upper portion. One film of the second flattening film 17 selected from among is thickly applied.
이후, 도 1f에 도시된 바와 같이, 활성영역(11a)의 상단부 표면이 노출될 때까지 제2평탄화막(17)에 대하여 HF 용액, 또는, 버퍼드 HF 용액을 이용한 습식 식각이나, 플라즈마를 이용한 건식 식각, 또는, CMP(Chemical Mechanical Polishing) 공정을 실시한다.Then, as shown in FIG. 1F, the wet planarization using the HF solution, the buffered HF solution, or the wet etching using the plasma is performed on the second planarization layer 17 until the upper surface of the active region 11a is exposed. Dry etching or a chemical mechanical polishing (CMP) process is performed.
이 결과, 반도체 기판(11)의 비활성영역에는 평탄화막이 매립되어 이루어진 소자 분리막들(20)이 형성되며, 이러한 소자 분리막들(20)에 의해 활성영역들(11a)은 전기적으로 분리된다.As a result, device isolation layers 20 formed by filling the planarization layer are formed in the inactive region of the semiconductor substrate 11, and the active regions 11a are electrically separated by the device isolation layers 20.
상기와 같은 공정을 통해 형성된 소자 분리막은 전체적으로 SOI 구조로된 기판에 형성한 것이기 때문에 이웃하는 활성영역들간의 누설전류의 흐름을 완전히 차단시킬 수 있다.Since the device isolation layer formed through the above process is formed on the SOI-structured substrate as a whole, the leakage current between neighboring active regions can be completely blocked.
또한, 열산화 공정시에는 활성영역을 둘러쌓고 있는 질화막에 의해 상기 활성영역에 스트레스가 인가되는 것을 방지할 수 있기 때문에 활성영역의 물성 및 전기적 특성의 저하를 방지할 수 있게 된다.In addition, during the thermal oxidation process, since the stress is applied to the active region by the nitride film surrounding the active region, it is possible to prevent deterioration of physical properties and electrical properties of the active region.
이상에서와 설명된 바와 같이, 본 발명은 SOI 기술을 응용하여 소자 분리막을 형성하기 때문에 활성영역의 물성 및 전기적 특성이 열화되는 문제와 활성영역이 잠식되는 문제를 방지할 수 있으며, 아울러, 소자들간의 전기적 분리를 안정적으로 수행할 수 있기 때문에 누설전류의 발생을 최대한 감소시킬 수 있게 되어 반도체 소자의 특성을 향상시킬 수 있다.As described above, the present invention can prevent the problem of deterioration of physical and electrical properties of the active region and the problem of encroachment of the active region because the device isolation layer is formed by applying SOI technology. Since the electrical separation can be performed stably, the generation of leakage current can be reduced as much as possible, thereby improving the characteristics of the semiconductor device.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
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