KR100545211B1 - A method for forming an isolation layer of a semiconductor device - Google Patents

Abstract

In the shallow trench isolation (STI) manufacturing process of the semiconductor device, the device isolation film of the semiconductor device to prevent the step difference generated on the surface of the field region and the active region after the chemical mechanical polishing (CMP) planarization It relates to a forming method. A device isolation film forming method of a semiconductor device according to the present invention includes the steps of: forming a pad oxide film and a nitride film on a semiconductor substrate; Forming a photoresist pattern on the nitride film to etch the nitride film and the pad oxide film, and to form a trench by etching a surface exposed portion of the semiconductor substrate to a predetermined thickness; Depositing a liner oxide over the entire surface along the trench inner interface to prevent damage to the trench; Depositing and planarizing a filler to sufficiently fill the trench; Selectively etching the filler in the planarized trench to the bottom of the nitride film; And removing the nitride film. According to the present invention, the wafer yield can be improved by minimizing the step difference of the field oxide film generated during the CMP planarization process in the STI manufacturing process, thereby eliminating the process defect due to the step difference in the subsequent process.

Device Isolation, Shallow Trench Isolation, STI, Field Area, Active Area, Step

Description

A method for forming an isolation layer of a semiconductor device

1A to 1G are flowcharts illustrating a method of forming a device isolation layer of a semiconductor device using the STI technique according to the related art.

2A to 2H are flowcharts illustrating a method of forming an isolation layer of a semiconductor device using the STI technique according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation layer of a semiconductor device, and more particularly, to a field trench and an active region after chemical mechanical polishing (CMP) planarization in a shallow trench isolation (STI) manufacturing process of a semiconductor device. The present invention relates to a device isolation film forming method of a semiconductor device for preventing a step occurring on the surface of an area.

In a semiconductor circuit, it is necessary to electrically isolate various elements such as transistors, diodes, and resistors formed on the semiconductor substrate. In addition, as the integration of semiconductor devices has progressed, fine patterns have been required in manufacturing devices, and the channel length of transistors and the width of field oxide films for device isolation have also been reduced.

As a method for forming such device isolation, a conventional LOCal Oxidation of Silicon (LOCOS) has been most commonly used.

The LOCOS device isolation is performed by sequentially forming a pad oxide film and a nitride film on a silicon substrate, patterning the nitride film, and selectively oxidizing the silicon substrate to form a field oxide film. In the selective oxidation of the silicon substrate, a bird's beak is generated at the end of the field oxide layer as oxygen penetrates into the side of the pad oxide layer under the nitride layer used as a mask. Since the field oxide film is extended to the active region by the length of the buzz beak by such a buzz beak, a so-called short channel effect is generated in which the channel length is shortened and the threshold voltage is increased, resulting in the electrical characteristics of the transistor. Worsens. In particular, the LOCOS device isolation exhibits limitations such as a punch-through occurs in which field oxide films on both sides of the active region are stuck as the channel length is reduced to 0.3 μm or less, thereby not accurately securing the width of the active region. It was.

Therefore, trench device isolation methods have been discussed in recent semiconductor manufacturing processes manufactured with design rules of 0.25 mu m or less. That is, a trench technique of partially etching the semiconductor substrate to form a predetermined trench between the devices and separating the devices is applied.

Recently, a silicon substrate is locally etched to form a trench during device isolation, and an insulating film (for example, an oxide film) is deposited, and an insulating film on the active region is etched by a chemical mechanical polishing (CMP) process. A shallow trench isolation (STI) technique is mainly used in which an insulating film remains only in the field region. In particular, the STI technique for forming the trench depth as shallow as 3 μm or less has been applied to a design rule of 0.15 μm or less without major problems.

The STI process may include forming a trench by etching a silicon substrate to a predetermined depth, depositing an insulating layer on the trench and the substrate, and etching the insulating layer by etching the entire surface by a back etching or a CMP method. Filling or filling the inside with an insulating film. Currently, undoped silicate glass (USG), tetra-ethyl-ortho-silicate (TEOS), high temperature oxide (HTO), or a combination thereof is used as an oxide film to fill a trench.

Hereinafter, a semiconductor device isolation process using the STI technique according to the prior art will be described in detail with reference to FIGS. 1A to 1G.

1A to 1G are process flowcharts illustrating a method of separating semiconductor devices using the STI technique according to the prior art.

First, a 100-200 kPa pad film 12 and a 1000-5000 kN nitride 13 are sequentially formed on the semiconductor substrate or silicon wafer 11 (see FIG. 1A).

Next, after the photoresist (PR) pattern 14 is applied onto the nitride film 13, the photoresist pattern 14 is exposed and developed to remove only the upper side of the device isolation region (see FIG. 1B). .

Next, the nitride film 13 and the pad oxide film 12 are etched using the photosensitive film pattern 14 as a mask, and then the photosensitive film pattern 14 is removed to expose a surface exposed portion of the semiconductor substrate 11. The trench is formed by etching a predetermined thickness (see FIG. 1C). That is, the nitride film 13, the pad oxide film 12, and the silicon substrate 11 are typically etched by a dry etching method to form trenches using the photoresist pattern 14, which has been selectively exposed and developed, as a mask. The trench thus formed is for forming a shallow trench isolation (STI) device, and reference numeral A denotes an etching portion where the trench is formed.

Next, to prevent the STI damage, an STI liner oxide 15 is deposited over the entire surface along the trench inner interface (see FIG. 1D). That is, the liner oxide film 15, which is a heat treatment process for improving the rounding of the lower corners and thermal stress, is performed at a thickness of about 100 to 300 kPa.

After that, a filler, for example, a tetra-ethyl-ortho-silicate (TEOS) oxide layer 16 is deposited to sufficiently fill the trench (see FIG. 1E). In other words, an oxide film deposition process for filling the trench gap is performed to a thickness of about 5,000 to 10,000 Pa using an AP (Atmospheric Pressure) Chemical Vapor Deposition (AP) method or a High Density Plasma (HDP) CVD method.

Next, the planarization operation is performed by a chemical mechanical polishing (CMP) process, followed by annealing to a predetermined temperature (see FIG. 1F). That is, the remaining packed oxide layer 16 except the trench is removed using the CMP planarization process, and the nitride layer 13 ′ is left at about 500 to 1500 kV using an end point detection (EPD). Here, reference numeral 16 'represents a portion where the trench filled with the trench is annealed.

Next, the nitride film 13 ′ is typically removed by wet etching to form an STI (see FIG. 1G), and a cleaning process is subsequently performed to complete the device isolation process.

However, the oxide film on the field region of the semiconductor device fabricated by the above-described STI process is about 100 to 300 kHz higher than the oxide film on the active region. This step affects subsequent processes, for example, gate patterning and etching. There is a problem that adversely affects the CD (Critical Dimension) uniformity (Uniformity) due to the step.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is a step difference between the surface area of a field region and an active region that occurs after planarizing STI by chemical mechanical polishing (CMP) in a method of manufacturing a semiconductor device having a shallow trench isolation (STI) structure. It is to provide a method for forming a semiconductor device isolation film that can prevent the.

As a means for achieving the above object, an element isolation film forming method of a semiconductor device according to the present invention,

Sequentially forming a pad oxide film and a nitride film on the semiconductor substrate;

Forming a photoresist pattern on the nitride film to etch the nitride film and the pad oxide film, and to form a trench by etching a surface exposed portion of the semiconductor substrate to a predetermined thickness;

Depositing a liner oxide over the entire surface along the trench inner interface to prevent damage to the trench;

Depositing and planarizing a filler to sufficiently fill the trench;

Selectively etching the filler in the planarized trench to the bottom of the nitride film; And

Removing the nitride film

It includes.

Here, the planarization of the filler may be performed by chemical mechanical polishing (CMP) so that only recesses of about 100 to about 200 kPa of the upper end of the nitride film are formed.

Here, the planarization of the filler may include stopping the planarization process by using end point detection (EPD) at the upper end of the nitride layer.

Here, the step of selectively etching the filler is characterized in that the filler is selectively removed using a HF solution or BHF solution diluted to 100: 1 to 200: 1.

Here, the selective etching of the filler may be performed by selectively etching the filler thickness of the field region and the nitride film thickness of the remaining active region.

In the selective etching of the filler, the filler may be selectively removed by dry etching such that the selectivity between the nitride layer and the filler is 50: 1 or more.

The removing of the nitride layer may include removing the nitride layer by wet etching using phosphoric acid (H ₃ PO ₄ ).

According to the present invention, it is possible to maximize the yield of the wafer by minimizing the step difference between the surface of the field region and the active region occurring after CMP planarization when forming the STI of the semiconductor device to overcome the problems caused during the subsequent process.

Hereinafter, a method of forming an isolation layer of a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The present invention is to maximize the yield of the wafer by overcoming the problems caused during the subsequent process by minimizing the step after CMP planarization in the STI manufacturing process.

2A to 2H are flowcharts illustrating a method of forming an isolation layer of a semiconductor device using the STI technique according to the present invention.

First, a 100-200 mPa pad oxide film 22 and a 1000-5000 mW nitride film 13 are sequentially formed on a semiconductor substrate or silicon wafer 21 (see Fig. 2A).

Next, after the photosensitive film pattern 24 is applied onto the nitride film 13, the photosensitive film pattern 24 is exposed and developed to remove only the upper side of the device isolation region (see FIG. 2B).

Next, the nitride film 23 'and the pad oxide film 22' are etched using the photosensitive film pattern 24 as a mask, and then the photosensitive film pattern 24 is removed and the surface of the semiconductor substrate 21 'is removed. The exposed portion is etched to a certain thickness to form a trench (see FIG. 2C). In other words, the nitride film 23 ', the pad oxide film 22', and the silicon semiconductor substrate 21 'are typically etched by a dry etching method using the photoresist pattern 24 which has been selectively exposed and developed as a mask to form a trench. To form. The trench thus formed is for forming a shallow trench isolation (STI) device, and reference numeral B denotes an etched portion where the trench is formed.

Next, to prevent the STI damage, the STI liner oxide film 25 is deposited over the entire surface along the trench inner interface (see FIG. 2D), that is, a heat treatment process for improving the rounding and thermal stress of the lower corner. The oxide film 25 is formed to a thickness of about 100 to 300 Å.

Thereafter, a filler, for example, a TEOS oxide layer 26 is deposited to sufficiently fill the trench (see FIG. 2E). In other words, an oxide film deposition process for filling the trench gap is performed to a thickness of about 5,000 to 10,000 Pa using an AP (Atmospheric Pressure) Chemical Vapor Deposition (AP) method or a High Density Plasma (HDP) CVD method.

Substantially the process before CMP planarization is the same as in the prior art.

Next, the STI formed as described above is subjected to a planarization operation by a chemical mechanical polishing (CMP) process, and then annealing is performed at a predetermined temperature (see FIG. 2F). Specifically, when the filling oxide film 26 'is removed by the CMP planarization process, the process is stopped by using end point detection (EPD) at the upper end of the nitride film 23 ". At this time, the nitride film 23" Is removed by about 100 to 500 Å from the thickness previously deposited, and all of the filled oxide film in the field region is opened. Substantially, during the CMP planarization process, it is preferable to form a recess only up to about 100 to 200 microns at the top of the nitride film 23 ".

Next, in this state, the packed oxide film 26 "is selectively removed using an HF solution or a BHF solution diluted from 100: 1 to 200: 1 (see FIG. 2G). Proceed by calculating the thickness of 23 " and the filling oxide film 26 " in the field region. Alternatively, dry etching is performed in which the selectivity between the nitride film 23 " and the filling oxide film 26 " The filling oxide layer 26 "may be removed.

Then, the conventional (see Fig. 2h) by removing the nitride film (23 ") by using a phosphoric acid (H ₃ PO ₄₎ by a wet etching to form the STI, performing a cleaning process and subsequently to the separation STI device process You are done.

Therefore, as described above, the STI is formed to eliminate the step difference between the field region and the active region, thereby minimizing the influence on subsequent gate patterning and etching.

While the invention has been described above, these examples are intended to illustrate rather than limit this invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments are possible without departing from the technical details of the present invention. Therefore, the scope of protection of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.

According to the present invention, the wafer yield can be improved by minimizing the step difference of the field oxide film generated during the CMP planarization process in the STI manufacturing process, thereby eliminating the process defect due to the step difference in the subsequent process.

Claims (7)

In the device isolation film forming method of a semiconductor device, Sequentially forming a pad oxide film and a nitride film on the semiconductor substrate; Forming a photoresist pattern on the nitride film to etch the nitride film and the pad oxide film, and to form a trench by etching a surface exposed portion of the semiconductor substrate to a predetermined thickness; Depositing a liner oxide over the entire surface along the trench inner interface to prevent damage to the trench; Depositing and planarizing a filler to sufficiently fill the trench; Selectively etching the filler in the planarized trench to the bottom of the nitride film; And Removing the nitride film Device isolation film forming method of a semiconductor device comprising a. The method of claim 1, The planarization of the filler may be performed by chemical mechanical polishing (CMP) to planarize recesses up to about 100 to 200 microns on the top of the nitride layer. The method according to claim 1 or 2, The planarizing of the filler may include stopping the planarization process by using end point detection (EPD) at the upper end of the nitride layer. The method of claim 1, The selective etching of the filler may include selectively removing the filler using an HF solution or a BHF solution diluted to 100: 1 to 200: 1. The method of claim 1, And selectively etching the filler to selectively etch the filler by calculating the thickness of the filler in the field region and the thickness of the nitride layer in the remaining active region. The method of claim 1, The selective etching of the filler may include selectively removing the filler by dry etching such that the selectivity between the nitride film and the filler is 50: 1 or more. The method of claim 1, The removing of the nitride layer may include removing the nitride layer by wet etching using phosphoric acid (H ₃ PO ₄ ).

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