KR20040070703A - Isolation method in a semiconductor manufacturing device - Google Patents
Isolation method in a semiconductor manufacturing device Download PDFInfo
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- KR20040070703A KR20040070703A KR1020030006883A KR20030006883A KR20040070703A KR 20040070703 A KR20040070703 A KR 20040070703A KR 1020030006883 A KR1020030006883 A KR 1020030006883A KR 20030006883 A KR20030006883 A KR 20030006883A KR 20040070703 A KR20040070703 A KR 20040070703A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Abstract
Description
본 발명은 반도체 소자 분리 및 소자 형성 기술에 관한 것으로, 특히, 산화막을 보호하고 활성화 영역과 소자 분리 영역을 보호하는데 적합한 반도체 제조 장치에서의 소자 분리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device isolation and device formation techniques, and more particularly, to a device isolation method in a semiconductor manufacturing apparatus suitable for protecting an oxide film and protecting an active region and an isolation region.
반도체 소자의 고집적화가 진행되면서 반도체 소자 분리 기술은 보다 복잡해지고 있는 추세이다.As semiconductor devices have been highly integrated, semiconductor device isolation technologies are becoming more complex.
도 1a 내지 도 1d는 종래의 반도체 제조 장치에서의 소자 분리 과정을 도시한 공정 단면도이다.1A to 1D are cross-sectional views illustrating a device isolation process in a conventional semiconductor manufacturing apparatus.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판으로서 실리콘 기판(100)을 열산화하여 패드 산화막(pad oxide)(102)을 100Å∼200Å 성장시키고, 그 위에 하드 마스크(hard mask)막으로서 질화막(104)을 1500Å∼2000Å 형성한다.First, as shown in FIG. 1A, the silicon oxide substrate 100 is thermally oxidized as a semiconductor substrate to grow a pad oxide 102 to 100 to 200 microseconds, and a nitride film (hard mask) as a hard mask film is formed thereon. 104) is formed from 1500 kV to 2000 kV.
그런 다음, 이 질화막(104) 상부에 감광막(photo resist)(106)를 도포하고 반도체 소자분리용 마스크를 이용하여 감광막(106)을 노광 및 현상하여 반도체 소자의 활성 영역(active region)과 소자분리 영역(isolation region)을 정의하는 포토레지스트 패턴을 형성한다.Then, a photoresist 106 is applied over the nitride film 104, and the photoresist film 106 is exposed and developed using a mask for semiconductor device separation to separate active regions and devices from the semiconductor device. A photoresist pattern defining an isolation region is formed.
그리고, 도 1b에서는, 감광막 패턴(106)을 사용한 건식 식각(dry etch) 공정으로 적층된 질화막(104)과 패드 산화막(102) 및 실리콘 기판(100)을 소정 깊이, 예컨대, 3000Å∼5000Å로 식각한 후 포토레지스트 패턴을 제거함으로써 셸로우 트렌치 소자 분리막(STI : Shallow Trench Isolation)이 형성될 부위인 트렌치를 형성하게 된다.In FIG. 1B, the nitride film 104, the pad oxide film 102, and the silicon substrate 100 stacked by a dry etch process using the photosensitive film pattern 106 are etched to a predetermined depth, for example, 3000 μm to 5000 μm. Afterwards, the photoresist pattern is removed to form a trench, which is a region where a shallow trench isolation layer (STI) is to be formed.
계속해서 도 1c에 도시된 바와 같이, 상기 결과물에 트렌치가 매립되도록 갭필 절연막으로서 실리콘 산화막(SiO2)(108) 및 APCVD로 형성된 TEOS(tetraetylorthosilicate)(110)를 증착한다.Subsequently, as shown in FIG. 1C, a silicon oxide film (SiO 2 ) 108 and a TEOS (tetraetylorthosilicate) 110 formed of APCVD are deposited as a gapfill insulating film so that a trench is embedded in the resultant.
그런 후, 도 1d에 도시한 바와 같이, 질화막(104)이 드러날 때까지 갭필 절연막(110)을 화학적 기계적 연마(Chemical Mechanical Polishing : CMP)로 식각하여 그 표면을 평탄화한다. 그리고 나서, 인산 용액 등으로 질화막(104)을 제거하여 종래 기술에 의한 셸로우 트렌치 소자 분리막을 완성한다.Thereafter, as shown in FIG. 1D, the gap fill insulating film 110 is etched by chemical mechanical polishing (CMP) until the nitride film 104 is exposed to planarize the surface thereof. Then, the nitride film 104 is removed with a phosphoric acid solution or the like to complete the shallow trench device isolation film according to the prior art.
이때, 도 1d의 과정에서는, 도시한 바와 같이, 트렌치 상단의 양 부분이 평탄화의 영향으로 인해 리키지(leakage)(112)가 발생될 수 있다.At this time, in the process of FIG. 1D, a leakage 112 may be generated due to the effect of planarization of both portions of the upper portion of the trench.
즉, 종래의 STI 공정은 도 1d에 나타난 바와 같이, 산화막(110)과 질화막(104)을 세정하면서 활성화 영역과 소자 분리 영역의 경계면이 취약해져 게이트 산화막에 영향을 주어 다이오드 리키지에 영향을 줄 수 있다는 문제가 제기되었다.That is, in the conventional STI process, as shown in FIG. 1D, the interface between the active region and the device isolation region becomes weak while cleaning the oxide layer 110 and the nitride layer 104, which may affect the gate oxide layer and affect the diode package. Has been raised.
특히, 최근에 이용되는 셸로우 트렌치 분리 공정에서도 소자 분리시 리키지 문제가 매우 심각하게 대두되고 있는 실정이다.In particular, in the shallow trench isolation process that is used recently, the problem of leakage in device isolation is very serious.
본 발명은 상술한 문제를 해결하기 위해 안출한 것으로, 트렌치 내부와 질화막 내부에 트렌치 내부 산화막을 형성함으로써, 반도체 세정 공정시 산화막의 손실을 방지하고 활성화 영역과 소자 분리 영역을 보호하여 수율을 높이도록 한 반도체 제조 장치에서의 소자 분리 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above-described problem, by forming a trench internal oxide film in the trench and the nitride film, to prevent the loss of the oxide film during the semiconductor cleaning process and to protect the activation region and the device isolation region to increase the yield It is an object of the present invention to provide a device isolation method in a semiconductor manufacturing apparatus.
이러한 목적을 달성하기 위한 본 발명의 바람직한 실시예에 따르면, 반도체 소자 분리 형성 방법에 있어서, 반도체 기판상에 패드(pad) 산화막, 감광막을 순차적으로 형성한 다음 패터닝 공정을 수행하는 단계와; 패드 산화막을 식각한 후 에슁(ashing) 및 세정(cleaning) 공정을 수행하는 단계와; 패드 산화막 상에 질화막을 증착한 다음 패드 산화막이 노출된 부분보다 넓게 패터닝하는 단계와; 질화막과 기판을 식각하고 에슁 및 세정 공정을 수행하여 트렌치를 형성하는 단계와; 산화 분위기에서 어닐링(annealing) 공정을 수행하여 트렌치 내부의 활성화 영역과 소자 분리 영역의 경계면에 내부(liner) 산화막을 형성하는 단계와; 트렌치 내부를 TEOS막 또는 NSG막으로 충진(full-fill)한 다음 질화막 표면까지 CMP하는 단계와; 인산을 이용하여 질화막을 제거하는 단계를 포함하는 반도체 제조 장치에서의 소자 분리 방법을 제공한다.According to a preferred embodiment of the present invention for achieving this object, a method of forming a semiconductor device, comprising: sequentially forming a pad oxide film, a photoresist film on a semiconductor substrate and then performing a patterning process; Etching the pad oxide film and then performing an ashing and cleaning process; Depositing a nitride film on the pad oxide film and then patterning the film wider than an exposed portion of the pad oxide film; Etching the nitride film and the substrate and performing an etching and cleaning process to form a trench; Performing an annealing process in an oxidizing atmosphere to form an inner oxide film on an interface between an active region inside the trench and an isolation region; Filling the inside of the trench with a TEOS film or an NSG film and then CMPing to the surface of the nitride film; A device isolation method in a semiconductor manufacturing apparatus comprising removing a nitride film using phosphoric acid.
도 1a 내지 도 1d는 종래의 반도체 제조 장치에서의 소자 분리 과정을 도시한 공정 단면도,1A to 1D are cross-sectional views illustrating a device isolation process in a conventional semiconductor manufacturing apparatus;
도 2a 내지 도 2i는 본 발명의 바람직한 실시예에 따른 반도체 제조 장치에서의 소자 분리 과정을 도시한 공정 단면도.2A to 2I are cross-sectional views illustrating a device isolation process in a semiconductor manufacturing apparatus according to a preferred embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
200 : 기판 202 : 제 1 산화막200 substrate 202 first oxide film
204, 208 : 감광막 206 : 질화막204 and 208: photosensitive film 206: nitride film
210 : 제 2 산화막 212 : 제 3 산화막210: second oxide film 212: third oxide film
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2i는 본 발명의 바람직한 실시예에 따른 반도체 제조 장치에서의 소자 분리 과정을 도시한 공정 단면도이다.2A to 2I are cross-sectional views illustrating a device isolation process in a semiconductor manufacturing apparatus according to a preferred embodiment of the present invention.
먼저, 도 2a에 도시한 바와 같이, 반도체 기판으로서 실리콘 기판(200)을 열산화하여 제 1 산화막, 예컨대, 패드 산화막(202)을 50 내지 300Å 두께로 성장시킨다.First, as shown in FIG. 2A, the silicon substrate 200 is thermally oxidized as a semiconductor substrate to grow a first oxide film, for example, the pad oxide film 202, to a thickness of 50 to 300 Å.
그런 다음, 도 2b에서는 이 패드 산화막(202) 상부에 감광막(204)을 도포하고, 후속되는 트렌치 형성 크기 만큼 감광막(204)이 노출되도록 패터닝한다.Then, in FIG. 2B, a photoresist film 204 is applied over the pad oxide film 202, and patterned so that the photoresist film 204 is exposed by a subsequent trench formation size.
도 2b의 공정 진행 후, 도 2c에서는 이러한 감광막(204)을 패턴으로 하여 패드 산화막(202)을 식각한 다음, 에슁 및 세정 공정을 수행하여 감광막(204)을 제거한다.After the process of FIG. 2B is performed, in FIG. 2C, the pad oxide film 202 is etched using the photoresist 204 as a pattern, and then the photoresist 204 is removed by performing an etching and cleaning process.
그런 후, 도 2d에서는 패드 산화막(202)과 실리콘 계면이 드러난 부분위에 질화막(206)을 500 내지 3000Å 두께로 증착한 다음, 감광막(208)을 도포하여 패드 산화막(202)이 드러난 부분보다 넓게 패터닝한다. 이때, 감광막(208)의 패터닝 폭은 후속되는 소자 분리 영역 폭의 101 내지 250%로 설정되는 것이 바람직하다.Then, in FIG. 2D, the nitride film 206 is deposited to a thickness of 500 to 3000 Å on the exposed portion of the pad oxide film 202 and the silicon interface, and then the photosensitive film 208 is applied to pattern the pattern wider than the exposed portion of the pad oxide film 202. do. At this time, the patterning width of the photosensitive film 208 is preferably set to 101 to 250% of the width of the subsequent isolation region.
도 2e에서는 도 2d에서 증착된 질화막(206)을 식각한다. 이때, 도 2e의 공정에서는, 산화막(202)과 질화막(206)간의 선택비를, 예컨대, 5:1 이상으로 설정하는 것이 바람직한데, 도시한 바와 같이, 산화막(202)의 식각을 방지하고 질화막(206)만을 식각하기 위해서 불소(F)기가 포함된 식각가스를 사용하지 않는 것을 특징으로 한다.In FIG. 2E, the nitride film 206 deposited in FIG. 2D is etched. At this time, in the process of FIG. 2E, it is preferable to set the selectivity ratio between the oxide film 202 and the nitride film 206 to, for example, 5: 1 or more. As illustrated, the etching of the oxide film 202 is prevented and the nitride film is prevented. In order to etch only (206), it is characterized in that the etching gas containing fluorine (F) group is not used.
한편, 도 2f에서는, 실리콘 기판(200)을 식각하고 에슁 및 세정 공정을 수행하여 감광막(208)을 제거함으로써 소자 분리 영역(트렌치)을 형성한다. 이때, 트렌치의 깊이는 1500 내지 5500Å이 바람직하며, 실리콘 기판(200)을 식각시 패드 산화막(202)이 식각되지 않도록 실리콘 기판(200)과 패드 산화막(202)의 선택비를 10:1 이상으로 설정한다.Meanwhile, in FIG. 2F, an isolation region (a trench) is formed by etching the silicon substrate 200 and performing an etching and cleaning process to remove the photosensitive film 208. In this case, the depth of the trench is preferably 1500 to 5500 Pa, and the selectivity ratio between the silicon substrate 200 and the pad oxide layer 202 is 10: 1 or more so that the pad oxide layer 202 is not etched when the silicon substrate 200 is etched. Set it.
이후, 도 2g에서는 트렌치 하부의 코너 부분의 리키지 감소를 위하여 트렌지 내부와 질화막(206) 외부에 제 2 산화막, 즉, 트렌치 내부 산화막(Liner 산화막)(210)을 형성하고, 이러한 내부 산화막(210)이 형성된 트렌치 내부를 제 3 산화막, 예컨대, TEOS막 또는 NSG막(212)으로 충진한다.Next, in FIG. 2G, a second oxide film, that is, a trench oxide film (Liner oxide film) 210, is formed inside the trench and outside the nitride film 206 to reduce the leakage of the corner portion of the lower trench. The inside of the trench in which the 210 is formed is filled with a third oxide film, for example, a TEOS film or an NSG film 212.
이때, 제 2 산화막(210)은 산화 분위기에서 노(furnace)로 어닐링을 하되, 그 두께는 100 내지 500Å 정도가 바람직하다. 또한, 제 3 산화막(212)은 APCVD 또는 PECVD 기법을 이용하여 TEOS 또는 NSG막을 형성하는데, 그 두께는 5000 내지 10000Å이고 노를 이용하여 치밀하게 충진한다.At this time, the second oxide film 210 is annealed in a furnace (furnace) in an oxidizing atmosphere, the thickness is preferably about 100 to 500Å. In addition, the third oxide film 212 forms a TEOS or NSG film using APCVD or PECVD techniques, the thickness of which is 5000 to 10000 kPa and is densely packed using a furnace.
이러한 공정 과정이 진행되고 난 다음, 도 2h에 도시한 바와 같이, CMP 기법을 이용하여 질화막(206) 표면까지, 바람직하게는 질화막(206) 전체 두께의 10 내지 90%가 남을 때 까지 제 3 산화막(212)을 평탄화한다. 이러한 제 3 산화막(212)은, 보다 바람직하게는, 1500 내지 6000Å의 두께를 지니도록 평탄화할 수 있다.After the process is performed, as shown in FIG. 2H, the third oxide film is formed to the surface of the nitride film 206 by using the CMP technique, preferably until 10 to 90% of the total thickness of the nitride film 206 remains. Flatten 212. More preferably, the third oxide film 212 can be flattened to have a thickness of 1500 to 6000 GPa.
이때, 이러한 평탄화 과정은, 예컨대, 엔드 포인트 장비(EPD : End Point Detector)를 이용하여 산화막(TEOS, NSG)에서 질화막이 나타나는 시점(EOP : End of Point)을 기준으로 EOP±20% 이내에서 조절함으로써 구현될 수 있다.In this case, the planarization process is controlled within EOP ± 20% based on the point of time (EOP: End of Point) of the nitride film (TEOS, NSG) using, for example, an end point detector (EPD). Can be implemented.
끝으로, 도 2i에서는 인산을 이용하여 질화막(206)을 제거함으로써, 소자 분리 영역과 활성화 영역을 형성한다. 이때, 소자 분리 영역의 잔여 두께는 1550 내지 6500Å이 바람직하며, 질화막(206)을 제거한 후에도 제 1 산화막이 50 내지 300Å 잔존하도록 구현하는 것이 바람직할 것이다.Lastly, in FIG. 2I, the nitride film 206 is removed using phosphoric acid to form an isolation region and an activation region. In this case, the remaining thickness of the device isolation region is preferably 1550 to 6500 GPa, and it may be preferable to implement the first oxide film to remain 50 to 300 GPa even after the nitride film 206 is removed.
결론적으로, 도 2i에 나타난 바와 같이, 게이트 산화막 형성 후 트렌치 상단 양쪽 끝부분의 모양이 종래와 같은 버드 비이크(Bird's beak) 형상이 아니기 때문에, 리키지가 발생되지 않음을 알 수 있을 것이다.In conclusion, as shown in FIG. 2I, since the shape of both ends of the upper end of the trench after the formation of the gate oxide layer is not the shape of a bird's beak as in the related art, it can be seen that no leakage occurs.
따라서, 본 발명은 활성화 영역과 소자 분리 영역의 산화막을 보호함으로써, 게이트 산화막이 형성되었을 때 소자의 신뢰성과 수율 향상을 기대할 수 있다.Therefore, the present invention can be expected to improve the reliability and yield of the device when the gate oxide film is formed by protecting the oxide film of the active region and the device isolation region.
이상, 본 발명을 실시예에 근거하여 구체적으로 설명하였지만, 본 발명은 이러한 실시예에 한정되는 것이 아니라, 후술하는 특허청구범위내에서 여러 가지 변형이 가능한 것은 물론이다.As mentioned above, although this invention was demonstrated concretely based on the Example, this invention is not limited to such an Example, Of course, various deformation | transformation are possible for it within the following Claim.
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