JPH05129424A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a dielectric isolation structure, and make it possible to form a vertical type transistor. CONSTITUTION:A low concentration N-type silicon substrate 14 being a first semiconductor substrate and a high concentration N-type silicon substrate 17 being a second semiconductor substrate are bonded so as to sandwich an SiO2 layer 16. V-type trenches 18 are formed on the silicon substrate 14 An SiO2 film 19 is formed on the wall surface of the trench 18. A poly silicon layer 20 is buried in the trench 18. Hence the silicon substrate 14 is isolated to be in island regions 21, 22. In the silicon substrate 14, an aperture part 23 is formed, in which a low concentration N-type epitaxial growth layer 24 having the silicon substrate 17 as the substratum is formed. A vertical type transistor can be formed by using the epitaxial growth layer 24 and the silicon substrate 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for use in manufacturing a semiconductor integrated circuit device including a logic circuit and an output transistor, such as a drive circuit device for a brushless DC motor, and a manufacturing method thereof. It is a thing.

[0002]

2. Description of the Related Art As a semiconductor device of this type, a device whose sectional view is shown in FIG. 5 has been proposed. In FIG. 5, 1 and 2 are low-concentration N-type silicon substrates and 3 respectively.
Is a high-concentration N-type layer formed on the silicon substrate 1, 4 is a SiO ₂ layer formed on the silicon substrate 3, and these silicon substrates 1 and 2 are joined with the SiO ₂ layer 4 sandwiched therebetween. Reference numeral 5 denotes a groove having a V-shaped cross section (hereinafter referred to as V groove) formed in the silicon substrate 1. The V groove 5 has a SiO ₂ layer 6 formed on the wall surface thereof, and polysilicon is provided inside the V groove. The layer 7 is buried and the silicon substrate 1 is
It is separated into 9 and 10.

Such a semiconductor device has a silicon substrate 1
SiO ₂ layer 6 formed on the SiO ₂ layer 4 and the V-groove 5 formed in the
Is intended to separate the dielectrics of the island-shaped regions 8, 9 and 10, and FIG. 6 shows an example of a semiconductor integrated circuit device formed by using such a semiconductor device. In FIG. 6, a CMOSFET 11 forming a logic circuit is formed in the island region 8, an NPN bipolar transistor 12 forming an analog circuit is formed in the island region 9, and an NPN bipolar transistor 13 forming an output transistor is formed in the island region 10. There is.

[0004]

In the semiconductor device of FIG. 5, since the silicon substrates 1 and 2 are insulated by the SiO ₂ layer 4, it is impossible to form a vertical transistor, so that a uniform operation is not possible. Even an output transistor that needs to take out a large amount of current has a problem in that it can be configured only horizontally as shown in FIG. By the way, if the output transistor is configured horizontally,
Not only is it difficult to extract a large current, but a potential gradient occurs between the portion near the collector electrode and the portion far from the collector electrode, which causes a problem that the transistor operation becomes nonuniform.

Therefore, the present invention has a dielectric isolation structure and enables formation of a vertical transistor,
Semiconductor device capable of manufacturing a logic element and an analog element, which are dielectrically separated, and an output transistor capable of extracting a large current under uniform operation, and a method of manufacturing the same It is intended to provide.

[0006]

A semiconductor device according to the present invention will be described in terms of its constituent elements with reference to FIG. 1 showing an embodiment. First, the semiconductor device has a dielectric structure and an opening 23 is formed. Semiconductor substrate 14, a second semiconductor substrate 17 joined to the first semiconductor substrate 14, and a second semiconductor substrate 1
7 as an underlying substrate and an epitaxial growth layer 24 formed in the opening 23.

The manufacturing method of the present invention includes the following steps (A) to (G). (A) A step of forming a high-concentration impurity layer of the same conductivity type as that of the first semiconductor substrate on the one main surface side, and forming an insulating film on the surface of the first semiconductor substrate; A step of joining the second semiconductor substrate to the first semiconductor substrate via the insulating film, and (C) partially forming an opening having a depth reaching the second semiconductor substrate from the first semiconductor substrate side. A step of (D) epitaxially growing a semiconductor layer of the same conductivity type as the second semiconductor substrate in the opening, (E) a V-shaped cross section having a depth reaching the insulating film in the first semiconductor substrate A step of partially forming a groove,
(F) After forming a thermal oxide film on the surface, depositing a semiconductor film or an insulating film on the thermal oxide film to a thickness that fills the V-shaped groove, (G) the semiconductor other than in the groove Removing the film or insulating film, and also removing the thermal oxide film to expose the first semiconductor substrate

[0008]

Since the epitaxial growth layer 24 formed in the opening 23 and the second semiconductor substrate 17 are not separated by the insulating layer, a vertical transistor can be formed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of one embodiment will be described with reference to FIG. In FIG. 1, 14 is a low-concentration N-type silicon substrate which is a first semiconductor substrate, 15 is a high-concentration N-type layer formed on the silicon substrate 14, and 16 is SiO ₂ formed on the high-concentration N-type layer 15. The layer 17 is a high-concentration N-type silicon substrate which is the second semiconductor substrate, and the silicon substrates 14 and 17 are bonded to each other with the SiO ₂ layer 16 interposed therebetween. 18
Is a V groove formed in the silicon substrate 14,
A SiO ₂ layer 19 is formed on the wall surface of the groove 18, and a polysilicon layer 20 is buried inside the V groove 18 to separate the silicon substrate 14 into island regions 21 and 22. Reference numeral 23 denotes an opening formed in the silicon substrate 14, and a low concentration N-type epitaxial growth layer 24 using the silicon substrate 17 as a base substrate is formed in the opening 23.

Next, a method of manufacturing this embodiment will be described with reference to FIGS. (A) A low-concentration N-type silicon substrate 14 is prepared, a high-concentration N-type layer 15 is formed on one main surface of the silicon substrate 14, and then a SiO ₂ layer 16 by thermal oxidation is formed on the high-concentration N-type layer 15. Form. (B) A high-concentration N-type silicon substrate 17 is prepared, and the silicon substrate 17 and the silicon substrate 14 are bonded with the SiO ₂ layer 16 sandwiched therebetween. (C) The upper surface of the silicon substrate 14 is polished to a required thickness.

(D) An opening 23 is formed in the silicon substrate 14 to partially expose the surface of the silicon substrate 17. (E) A low concentration N-type epitaxial growth layer 24 using the silicon substrate 17 as a base substrate is formed in the opening 23. (F) A V groove 18 having a depth reaching the SiO ₂ layer 16 is formed in the silicon substrate 14. (G) A SiO ₂ layer 19 is formed by thermal oxidation on the entire surface side including the wall surface of the V groove 18, and thereafter, a polysilicon layer 25 is further deposited on the entire surface side to form a polysilicon layer in the V groove 18. Fill 20.

Next, the polysilicon layer 25 is polished so as to leave the polysilicon layer 20 in the V groove 18, and further, SiO 2 is formed.
Remove the SiO ₂ layer portion and the SiO ₂ layer portion on the epitaxial growth layer 24 of the silicon substrate 14 of the _second layer 19, to expose the upper surface of the top and the epitaxial growth layer 24 of the silicon substrate 14. As a result, the semiconductor device of this embodiment shown in FIG. 1 is formed.

FIG. 4 shows an example of a semiconductor integrated circuit device constructed by using the semiconductor device of the embodiment shown in FIG. In FIG. 4, the CMO forming the logic circuit in the island region 21.
An SFET 11 is formed, and an NPN bipolar transistor 12 forming an analog circuit is formed in the island region 22. The epitaxial growth layer 24 and the silicon substrate 17 are used, and the collector electrode 26 is provided on the back surface of the silicon substrate 17 to form the output transistor 27 which is an NPN bipolar transistor.

As described above, according to this embodiment, the vertical N
There is an effect that the output transistor 27 composed of a PN bipolar transistor can be configured and each circuit element can be separated by the dielectric material, that is, the SiO ₂ layers 16 and 19. Although the above embodiment has described the case where the output transistor 27 formed of the vertical NPN bipolar transistor is formed, the present invention also applies to the case where the vertical PNP bipolar transistor is formed as the output transistor or the vertical MOS.
It can also be applied when forming a FET.

[0015]

According to the present invention, a dielectric isolation structure is formed on a first semiconductor substrate, an opening is formed in the first semiconductor substrate, and a second semiconductor substrate is formed in the opening as a base substrate. By adopting the configuration of providing the epitaxial growth layer as
Since it is possible to form a vertical transistor by using the semiconductor substrate of, the use of the present invention makes it possible to take out a large current under uniform operation together with a logic element and an analog element which are dielectrically separated. There is an effect that it is possible to manufacture a semiconductor integrated circuit device having an output transistor that can be manufactured. Further, according to the manufacturing method of the present invention, two semiconductor substrates are bonded to each other, an opening is formed from one semiconductor substrate, and an epitaxial growth layer having the other semiconductor substrate as a base substrate is formed in the opening. Since two semiconductor substrates form a continuous semiconductor region,
A semiconductor device capable of forming a vertical transistor can be manufactured by the already established process and by a relatively simple process.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a process sectional view showing a front half of a process for manufacturing the embodiment of FIG.

FIG. 3 is a process sectional view showing a latter half of the process for manufacturing the embodiment of FIG.

4 is a sectional view showing an example of a semiconductor integrated circuit device using the embodiment of FIG.

FIG. 5 is a sectional view showing an example of a conventional semiconductor device.

6 is a cross-sectional view showing a semiconductor integrated circuit device using the conventional example of FIG.

[Explanation of symbols]

14 low-concentration N-type silicon substrate (first semiconductor substrate) 17 high-concentration N-type silicon substrate (second semiconductor substrate) 23 opening 24 epitaxial growth layer

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 29/73 29/784 9168-4M H01L 29/78 321 R

Claims (2)

[Claims] 1. A first semiconductor substrate having a dielectric isolation structure and having an opening formed therein, a second semiconductor substrate bonded to the first semiconductor substrate, and the second semiconductor substrate. And an epitaxial growth layer formed in the opening as a base substrate. 2. A method of manufacturing a semiconductor device including the following steps (A) to (G). (A) A step of forming a high-concentration impurity layer of the same conductivity type as that of the first semiconductor substrate on the one main surface side, and forming an insulating film on the surface of the first semiconductor substrate; A step of joining the second semiconductor substrate to the first semiconductor substrate via the insulating film, and (C) partially forming an opening having a depth reaching the second semiconductor substrate from the first semiconductor substrate side. (D) a step of epitaxially growing a semiconductor layer of the same conductivity type as that of the second semiconductor substrate in the opening, (E) a V-shaped cross section having a depth reaching the insulating film in the first semiconductor substrate A step of partially forming a groove, (F) a step of forming a thermal oxide film on the surface, and then depositing a semiconductor film or an insulating film on the thermal oxide film to a thickness to fill the V-shaped groove, G) The semiconductor film or insulating film other than in the groove is removed, and the thermal oxide film is also removed. Exposing the first semiconductor substrate and removed by.