JPS6334949A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to reduce the collector resistance value of a bipolar transistor formed on a substrate by a method wherein a substrate whose high-density region has been formed in advance on an adhesion plane is bonded to another substrate via an insulation film by means of a wafer-bonding technique. CONSTITUTION:A thermally oxidized film 22 is formed on an adhesion plane 21 on a first semiconductor substrate 20 of N type silicon, and is etched in a manner that a portion of the adhesion plane 21 is exposed for arsenic implantation to form an N<+> type silicon layer 23. In a sufficiently clean atmosphere thermally oxidized films 26 and 27 are formed both on the adhesion plate 21 on the first semiconductor substrate 20 where the thermally oxidized film 22 has been removed and on an adhesion plane 25 on the second semiconductor substrate 24 of N<+> type silicon. The thermally oxidized films 26 and 27 are then attached closely together, and are heat-treated. Through an oxide film 28 which is formed by uniting these films, a composite substrate is obtained after the films 26 and 27 are firmly attached together in such a way that two mirror surfaces are attached. Then, a groove is formed so that it can reach the oxide film 28. After an oxide film 29 has been formed on the inside surface of the groove and polycrystalline silicon 30 has been deposited, an island region 31 having an N<+> buried layer 23 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to a semiconductor device requiring isolation between elements.

(Prior Art) Conventionally, in a semiconductor device in which a plurality of active elements or passive elements are integrated on one substrate, it is necessary to electrically isolate the elements from each other. The device isolation methods used for this purpose include those using a reverse biased PN junction and those using an insulator. FIG. 4 shows an example of a semiconductor substrate having regions separated by a PN junction. An N-type epitaxial layer 2 is deposited on a P-type semiconductor substrate 1, and a door-type diffusion is performed on this epitaxial layer 2 to form an element isolation region 3 reaching the semiconductor substrate 1. As a result, an island-like region 4 surrounded by PN junctions is obtained. When an NPN transistor is formed in this island region, an N type epitaxial layer 2 is usually grown after an N+ type diffusion region 5 is formed for the purpose of lowering the collector resistance. This element region 4 is electrically isolated from other epitaxial layer portions via a depletion layer by applying a reverse bias to the PN junction. However, when forming the r-type device isolation region 3, lateral diffusion of approximately the same size as the depth direction inevitably occurs, resulting in an increase in the required area of the device isolation region 3. In addition, this PN junction isolation is used by applying a reverse bias, but in this case the P-type element region 3 is usually grounded, so the N-type layer in the element region 4 that is in contact with this region must always be held at a positive potential. There is. This imposes restrictions on the bias circuit of the integrated circuit formed in the element region 4, and an extremely complicated bias circuit is required, for example, when forming transistors of different conductivity. Furthermore, in PN junction isolation, parasitic elements are generally likely to be formed.For example, a space layer 6 is formed in the element region 4 as shown in FIG. When an NPN transistor is formed by providing an emitter layer 7 and a collector electrode point 8, a parasitic transistor is formed in which the base layer is the emitter, the N-type island region and the N-buried layer are the base, and the P-type substrate 1 is the collector.

Next, FIG. 6 shows one conventional example of element isolation using an insulator.

The device region consisting of the N-type semiconductor 9 and the N-buried layer 10 is
A silicon oxide film 1 and a polycrystalline silicon layer 12 form an island region that is separated and held. This method uses the P
There are advantages such as no need for a reverse bias circuit required for N-junction isolation, and fewer restrictions due to parasitic elements. However, in this method, the substrate is made of polycrystalline silicon, which requires a very thick substrate, which is disadvantageous economically.Also, since one side of the semiconductor substrate is insulated, it is difficult to It cannot be used as an escape route.

(Problems to be Solved by the Invention) There is a silicone bonding technique that improves the structural and economical drawbacks of the above two types of element isolation techniques.

FIG. 7 shows an example of an element isolation structure using this urethane bonding technique. Mirror-finished insulating films 15 and 16 are formed on the surfaces of the Nu semiconductor 13 and the N-type semiconductor 14, respectively, and then bonded, and the N-type semiconductor 13 is polished to a predetermined thickness. Then, an etched portion reaching at least the insulating film 15 is formed on a part of the surface of this N-type semiconductor 13, and after forming an insulating film 17 on the inner surface of the etched portion, polycrystalline silicon 18 is deposited, thereby forming an element. Area 19 is obtained.

The element isolation structure using this adhesive technique has the advantage of having few parasitic effects and being economically inexpensive. Also,
Since the N-type silicon on the back side has a high thermal conductivity, it is particularly advantageous when a high-power device is formed on this substrate.

However, when an NPN transistor is formed in this element isolation region, there is a drawback that the collector resistance increases and the saturation voltage increases because there is no N buried layer.

An object of the present invention is to provide a semiconductor device having a structure in which an insulator-separated substrate (composite semiconductor substrate) obtained by bonding two semiconductor substrates through an insulating film is provided with a high-concentration buried layer having the same conductivity as the substrate. This is what we provide.

(Means and effects for improving the problems) In the semiconductor device of the present invention, a substrate on which a high concentration region has been formed in advance on the bonding surface is bonded to another substrate via an insulating film using wafer bonding technology. Obtained by gluing. In particular, when forming a pie-I-La transistor on this substrate, having the above-mentioned high concentration region has advantages such as significantly lowering the collector resistance compared to a conventional bonded type insulator-separated substrate. be.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure shows an example of the manufacturing process of the semiconductor device of the same embodiment. First, as shown in FIG. A thermal oxide film 22 is formed on the surface 2, and the thermal oxide film 22 is etched using a known photo-etching technique,
A part of the surface 2 of the N-type silicon substrate 20 to be bonded is exposed.

Next, arsenic is injected into the bonded surface 21 of the N-type silicon substrate 20 using, for example, a known ion implantation method at an accelerating voltage of 40 k.
An N+ type silicon layer 23 is formed by implanting 5×10 15 m −2 of V. The N+ type silicon layer 23
Thermal diffusion of arsenic or antimony may be used to form the arsenic or antimony. Next, as shown in FIG. 1(B), the thermal oxide film 2
The bonded portion 21 of the first semiconductor substrate 20 from which N.
A thermal oxide film (insulating film) 26, 27 of approximately 1NL is formed in a sufficiently clean atmosphere on the mirror-finished surface 25 of the second semiconductor substrate 240 of type silicon with a surface roughness of 5001 or less. Next, the first semiconductor 2 is heated in a sufficiently clean atmosphere.
The thermal oxide film 26 formed on the surface to be bonded 21 of the second semiconductor 24 and the thermal oxide film 27 formed on the surface to be bonded 25 of the second semiconductor 24 are brought into close contact with each other, and heat treatment is performed to form the structure shown in FIG. 1C. By integrating the oxide films (insulating films) 26 and 27, a composite substrate with strong mirror surface bonding via the multi-formed oxide film (insulating film) 28 is obtained. The surface of this composite substrate on the first semiconductor substrate 20 side is polished, and the thickness a of the first semiconductor substrate 20 is adjusted depending on the withstand voltage of the element formed on this composite substrate. Furthermore, element isolation technology is applied to the composite substrate shown in FIG. 1 (Q) to obtain an insulator separation substrate of a desirable embodiment shown in FIG. RIE (Reactive I) from the surface of 20
A continuous trench having a width of 4 to 5 .mu.m is formed up to at least the oxide film 28 by the on-etching method, and then an oxide film 29 is formed on the inner surface of the trench.

Subsequently, polycrystalline silicon 3υ is deposited in the trench and the surface is planarized to form an island region 31 having an N buried layer 23.

Incidentally, if a plurality of the above-mentioned contiguous element isolation regions are formed as desired, a plurality of element regions can be obtained. In addition, in the example, the element isolation region was formed by a dielectric isolation method using RIE to reduce the area required for the element isolation region.
If desired, a PN junction isolation method using a P-type region or a mesa etch isolation method may be employed. Furthermore, when it is desired to form a high concentration buried layer over the entire substrate, the process is further simplified and the photolithography process when forming the high N concentration region can be omitted. FIG. 2(A) shows a substrate of the present invention having a full-surface N high-concentration buried region. Further, FIG. 2(B) shows an example in which element isolation technology is applied to the substrate. In addition, when forming a vertical arm element on this substrate, as shown in Fig. 1 (C
') After forming an etched portion extending from the surface of the substrate to at least the N+ type semiconductor 24, a silicon layer with a desired impurity concentration is epitaxially grown, and the surface is planarized.
The above-described element isolation step may be performed. Figure 3 shows power M
An example is shown in which an O8FET, an NPN) transistor, and a C-MOS are formed on the substrate. 32 in Figure 3 is NPN)
Emitter of transistor, 33 is eN) Pace of transistor, 34 is NPN) Collector of transistor, 35 is N-channel MOS) Source of transistor, 36 is N-channel MOS) y-to of transistor, 37 is N-channel MOS transistor・Drain of Zostar, 38 is P-channel MO8) Source of transistor, 39 is P-channel MO
The dirt of the S transistor, 40 is the drain of the P-channel MO8) run-zoster, 41 is the source of the NOG2 MOS transistor, 42 is the dirt of the NOGWAR MO8) transistor, 43 is the epitaxial layer, 44 is the back electrode () 45 is an insulating film. Further, in this embodiment, a case has been described in which an N-type buried layer is formed on an N-type substrate, but it is obvious that a P-type buried layer can also be easily formed on a P-type substrate.

Furthermore, in this embodiment, the bonding is performed with the insulating film present on both the first semiconductor substrate and the second semiconductor substrate, but the insulating film is present only on one of the semiconductor substrates, and on the other. Adhesion is possible even when there is no insulating film,
The structure of the semiconductor device of the present invention can also be realized by the above method.

[Effects of the Invention] As described in detail above, by using the semiconductor substrate according to the present invention, it is possible to improve the saturation characteristics of bipolar transistors, which was a problem with insulator-separated substrates using conventional bonding methods. Furthermore, since no expensive epitaxial process is used, it has great economic advantages. When element isolation technology using an insulator is applied to the substrate of the present invention,
It is also possible to prevent latch-up of the CMO8 transistor. Furthermore, since the N-type silicon on the back surface has a high thermal conductivity, it is advantageous when forming a high-power device.

Furthermore, since the back surface can be used as a current path, it is very effective as a substrate for a power IC that combines a vertical high-power element, a control bipolar IC, and a CMO8 IC.

[Brief explanation of drawings]

Fig. 1 is a manufacturing process diagram of one embodiment of the present invention, Fig. 2 is a sectional view of another embodiment of the invention, Fig. 3 is a sectional view of still another embodiment of the invention, and Figs. FIG. 7 is a sectional view of a conventional device. 20... N-type first semiconductor substrate, 22... Oxide film, 2
3... N type silicon layer, 24... N type second semiconductor substrate, 26.27... Oxide film, 28... Oxide film,
29... Oxide film, 30... Polycrystalline silicon, 31.
...N-type island region.

Claims (5)

[Claims] (1) A composite semiconductor substrate is provided in which one main surface of a first semiconductor substrate and one main surface of a second semiconductor substrate are directly bonded via an insulator, and the bonding surface side of the first semiconductor substrate is provided. 1. A semiconductor device comprising a region having the same conductivity type as the first semiconductor substrate and having a higher concentration than the first semiconductor substrate. (2) The semiconductor device according to claim 1, wherein the first semiconductor substrate is separated into a plurality of regions by dielectric separation. (3) The semiconductor device according to claim 1, wherein the first semiconductor substrate is separated into a plurality of regions by PN junction separation. (4) The semiconductor device according to claim 1, wherein the first semiconductor substrate is separated into a plurality of regions by mesa etch. (5) At a selected location of the composite semiconductor substrate, the first
2. The semiconductor device according to claim 1, wherein the semiconductor substrate and the second semiconductor substrate are communicated with each other to form a power element.