JP2971408B2 - Manufacturing method of dielectric isolation substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation technology, and more particularly, to a method for manufacturing a dielectric isolation substrate in which two wafers are bonded via an insulating film.

[0002]

2. Description of the Related Art Conventionally, there has been known a method utilizing a direct bonding technique of a wafer in order to realize dielectric isolation. In this method, as shown in FIG. 3, two silicon wafers 1 and 2 are bonded via an SiO ₂ film 3, a V-groove 4 is dug in the wafer 2, and an oxide film 5 is formed on a side surface of the groove 4. As a result, the silicon single crystal islands are dielectrically separated. However, in this structure, when MOS is used as the logic, many MOS logics can be created in the same island, but in order to use the bipolar element as the logic, it is necessary to separate each logic one by one by a V groove. It is not suitable under the current situation where the V-groove occupies a large area.

When both a low breakdown voltage element (for example, a bipolar element) and a high breakdown voltage element (for example, a DMOS element) are formed on a dielectric isolation substrate as shown in FIG. 3, there are the following problems. That is, to form a DMOS element, it is necessary to make the substrate relatively thick in order to obtain a high breakdown voltage, and to form a bipolar element, it is necessary to make the substrate thin in order to obtain high speed. It has been difficult to achieve the desired substrate thickness for both elements.

In order to make the element formation substrate for a bipolar transistor sufficiently thin, it is necessary to polish the silicon wafer 2 for a long time to make it thinner, and there is a problem that this polishing process takes much time.

[0005]

As described above, conventionally, when a DMOS element and a bipolar element are formed on a dielectric isolation substrate, it is necessary to separate the DMOS element and the bipolar element one by one by a groove. There is a problem that the number of elements increases and the element formation area decreases. Further, when forming a DMOS element and a bipolar element, it has been difficult to realize an optimum substrate thickness for both of them as a dielectric isolation substrate.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a dielectric isolation substrate suitable for forming a high breakdown voltage element and a low breakdown voltage element. It is in.

[0007]

[Means for Solving the Problems]

(Structure) In order to achieve the above object, the present invention employs the following structure and method.

That is, according to the present invention, in a method of manufacturing a dielectric isolation substrate, a step of bonding a high-resistance (first or second conductivity type) second silicon wafer on a first silicon wafer via an insulating film. Forming a high-concentration impurity buried layer (of the second conductivity type) on the surface of the second silicon wafer by diffusion; and forming a low-concentration impurity (of the second conductivity type) epitaxial layer on the second silicon wafer. Forming a layer, providing a groove extending from the surface of the epitaxial layer to the insulating film, separating the epitaxial layer and the second silicon wafer into islands, and embedding an insulating film in the groove. And characterized in that:

Here, preferred embodiments of the present invention include the following. (1) The second silicon wafer is polished and thinned before forming the epitaxial layer. (2) As a step of burying an insulating film in the groove, a polycrystalline silicon film is buried in the groove via an oxide film. (Function) According to the present invention, a high-concentration impurity buried layer is formed by diffusion, and a low-concentration epitaxial layer is formed thereon, so that the epitaxial layer substantially serves as a substrate for element formation. Can be made sufficiently thin. In this case, a polishing step or the like of the silicon wafer is not required, or the number of polishing steps is small, so that the manufacturing time and the manufacturing cost can be reduced. Further, if the buried layer is partially provided, the substantial thickness of the element forming substrate can be partially changed depending on the presence or absence of the buried layer, thereby forming a high breakdown voltage element and a low breakdown voltage element. It is possible to realize a dielectric isolation substrate suitable for the above.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device according to one embodiment of the present invention. This structure is a dielectric isolation using a trench. That is, p ^-
After forming an n ⁺ buried layer 511 partially on the active layer 502 ′ and further forming an n ⁻ epitaxial layer 504, a trench 505 is formed by RIE or the like. In a trench using RIE or the like, embedding and flattening with the thermal oxide film 506 and the polycrystalline silicon film 507 are easy, and the thickness of the n ⁻ epitaxial layer 504 can be kept almost the same before and after flattening. Also, since the buried n ⁺ layer 511 can be used, the n ⁻ epitaxial layer 504 at the logic level can be used.
Can be made thinner, and the performance of logic can be improved. on the other hand,
In the high breakdown voltage element portion, the depletion layer can be extended to the n ^- epitaxial layer 504 and the p ^- layer active 502 ', so that a high breakdown voltage can be obtained. In this embodiment, the n ⁺ layer may be diffused in the trench after the trench is formed. Further, an n ⁻ layer can be used as the active layer 502 ′.

FIG. 2 is a cross-sectional view showing a step of manufacturing the dielectric isolation substrate according to the embodiment. In this embodiment, a high-concentration impurity layer is formed on the second silicon wafer side to reduce the warpage of the dielectric isolation substrate.

As shown in FIG. 2A, a Si wafer 501 is provided.
And 502 are prepared, and at least one substrate is oxidized to form an oxide film 503. In the figure, the substrate 502 is oxidized. After these wafers 501 and 502 are directly bonded as shown in FIG. 2B, the thickness of the wafer 502 serving as an active layer is reduced by polishing. Next, as shown in FIG.
A high concentration impurity layer 511 is formed on the polished surface of the wafer 502 by a known diffusion technique. Further, an Si layer 504 is epitaxially grown on the high concentration impurity layer 511.

Next, as shown in FIG. 2D, a groove 505 is formed from the surface to the oxide film 503 to separate the active layer 502 and the epitaxial layer 504 into islands. Thereafter, as shown in FIG. 2E, an oxide film 506 is formed on the side surface of the groove 505 to electrically isolate the islands. Finally, the trench 505 is filled with a polycrystalline silicon film 507 or the like, and if necessary, the surface is flattened to obtain a dielectric isolation substrate.
Although the groove 505 is shown as a trench by RIE, it may be V-shaped or U-shaped by wet etching or the like.

With such a configuration, the warpage of the dielectric substrate when returning to room temperature after the heat treatment is reduced by the action of the high-concentration impurity layer 511. The reason will be described below.

Generally, when a high-concentration impurity layer is provided on the surface of a Si wafer, the wafer is warped. This is Si
And the covalent radius of the impurity atom is different, for example, p
In typical types of n and n-type boron and phosphorus, the diffused surface warps concavely.

On the other hand, the adhesive substrate is formed by integrating two wafers by heat treatment. When the temperature returns to room temperature after the heat treatment, stress is generated in both the silicon and the oxide film due to a difference in thermal contraction between the silicon and the oxide film. Since silicon has a larger thermal shrinkage than an oxide film, tensile stress acts on silicon at room temperature to shrink. Also, a compressive stress acts on the oxide film, and the oxide film is about to expand. Since the above-mentioned adhesive substrate makes the upper wafer thinner by polishing, the oxide film is above the center. For this reason, the substrate is warped upward, that is, toward the second wafer.

Therefore, if a high-concentration impurity layer is provided on the wafer surface above the adhesive substrate, the warpages cancel each other, and the warpage as a whole can be reduced. However, if a high-concentration impurity layer is formed on the surface, an element cannot be formed on this substrate.

Therefore, if a high-concentration impurity layer is provided inside the upper wafer as in this embodiment, the effect of reducing the warpage is not impaired, and an arbitrary element can be formed on the Si layer on the impurity layer. Can be. Further, the high concentration impurity layer is not limited to the inside of the active layer, and may be provided at the bottom of the active layer. In addition,
The thickness of the Si layer on the high-concentration impurity layer, that is, the depth of the high-concentration impurity layer can be arbitrarily set, but generally, depending on characteristics required for an element formed on the Si layer on the high-concentration impurity layer, It is determined.

The present invention is not limited to the above embodiments. For example, the conductivity types of the active layer and the epitaxial layer do not necessarily need to be opposite, and may be the same conductivity type. Similarly, the high breakdown voltage element and the low breakdown voltage element are pn
In the case of junction separation, the conductivity types of the active layer and the epitaxial layer need to be opposite conductivity types.However, in the case of dielectric separation, even if the conductivity types of the active layer and the epitaxial layer are the same conductivity type. Good. As the high breakdown voltage element and the low breakdown voltage element, various elements other than the MOS element and the bipolar element can be used. In addition, various modifications can be made without departing from the scope of the present invention.

[0020]

As described above in detail, according to the present invention, a high-concentration impurity buried layer is formed on a surface of a second silicon wafer by diffusion, so that a low-concentration epitaxial layer formed thereon is substantially formed. The substrate for element formation can be made sufficiently thin without requiring a long polishing step or the like. Further, by partially forming the buried layer, a dielectric isolation substrate suitable for forming a high breakdown voltage element and a low breakdown voltage element can be realized, and the element characteristics of a semiconductor element formed on this substrate can be improved. And so on.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a schematic configuration of a dielectric isolation substrate according to a first embodiment.

FIG. 2 is a sectional view showing a step of manufacturing the dielectric isolation substrate according to the first embodiment.

FIG. 3 is a sectional view showing a schematic configuration of a conventional dielectric isolation substrate.

[Explanation of symbols]

501: first silicon wafer 502: second silicon wafer 502 '... p ^- active layer 503 ... oxide film (insulating film) 504 ... n ^- epitaxial layer 505 ... trench groove (element isolation groove) 506 ... oxide film ( 507 ... polycrystalline silicon film 511 ... n ⁺ buried layer (high concentration impurity layer buried layer)

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kojiro Tanzawa 1 Toshiba Research Institute, Komukai, Kawasaki-shi, Kanagawa Prefecture (56) References JP-A-1-280333 (JP, A) Kaisho 49-15915 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/76 H01L 27/06 H01L 27/08

Claims (4)

(57) [Claims] 1. A step of bonding a high-resistance second silicon wafer on a first silicon wafer via an insulating film, and forming a high-concentration impurity buried layer on the surface of the second silicon wafer by diffusion. Forming a low-concentration impurity epitaxial layer on the second silicon wafer;
Forming a groove extending from the surface of the epitaxial layer to the insulating film, separating the epitaxial layer and the second silicon wafer into islands, and embedding an insulating film in the groove. Of manufacturing a dielectric isolation substrate. 2. A step of bonding a second silicon wafer of a first or second conductivity type on a first silicon wafer via an insulating film, and a step of bonding a second silicon wafer of a second conductivity type on a surface of the second silicon wafer. Forming a high concentration impurity buried layer by diffusion;
Forming a second conductivity type low-concentration impurity epitaxial layer on the second silicon wafer; and providing a groove extending from the surface of the epitaxial layer to the insulating film to form the epitaxial layer and the second silicon wafer into an island shape. A method for manufacturing a dielectric isolation substrate, comprising a step of separating and a step of burying and forming an insulating film in the groove. 3. The method for manufacturing a dielectric isolation substrate according to claim 1, wherein the second silicon wafer is polished and thinned before forming the epitaxial layer. 4. The dielectric isolation substrate according to claim 1, wherein said step of burying an insulating film in said groove comprises burying a polycrystalline silicon film in said groove via an oxide film. Production method.