JP2979554B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which bipolar transistors are integrated.

[Prior art] Conventionally, separation of elements in a bipolar IC
As shown in FIG. 18, this is performed by PN junction. That, N after forming the buried N ⁺ region 1 ^- epitaxial Kitaki interstitial region 2 is formed, N ^- therearound to form a device in the epitaxial region 2 arranged isolation region (P ⁺ region) 3 I was Furthermore, elements (transistors)
, A deep N ⁺ region 4 is formed to lower the saturation voltage Vsat.

[Problems to be Solved by the Invention] However, it is necessary to form an isolation region (P ⁺ region) 3 around the element for insulating and isolating the element.
This was an obstacle to miniaturization. In order to form a deep N ⁺ region 4 around the element in order to lower the saturation voltage Vsat, it is necessary to provide a gap between the deep N ⁺ region 4 and the isolation region (P ⁺ region) 3. At the time of ion implantation and subsequent annealing, the deep N ⁺ region 4 also spreads in the lateral direction, so that the area occupied by the element (transistor) has increased. In addition, there is a problem that the buried N ⁺ region 1 also expands during this annealing. Further, a mask for forming the buried N ⁺ region 1 was required, which increased the cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of performing isolation of a bipolar transistor, lowering a saturation voltage, and achieving miniaturization of a semiconductor device.

[Means for Solving the Problems] The invention according to claim 1, wherein a first step of arranging a semiconductor layer of a first conductivity type on a substrate via a high-concentration impurity region on a side facing the substrate; A second PN junction which forms a part of a semiconductor element between the first conductive type semiconductor layer and the first conductive type semiconductor layer on a surface which will later become an island region in the semiconductor layer of the first conductive type;
A second step of forming a conductive type diffusion region, and thereafter forming a trench from the surface of the first conductive type semiconductor layer to the substrate and defining a semiconductor element forming island region in the semiconductor layer; A third step of disposing a sidewall conductive region electrically connected to the high-concentration impurity region in the island region from the high-concentration impurity region to the surface of the semiconductor layer along an inner wall of the trench; A fourth step of forming an insulating layer on the inner wall of the trench so as to cover the outer periphery of the region.

In the invention described in claim 2, in claim 1, the third step is a step of diffusing impurities of the same conductivity type as the high-concentration impurity region from the inner wall of the trench to form the sidewall conductive region. The gist of the present invention is a method of manufacturing a semiconductor device.

According to a third aspect of the present invention, in the second aspect, the third step connects the high-concentration impurity region and the side wall conductive region also to a surface of the first conductive semiconductor layer in the island region. The present invention provides a method of manufacturing a semiconductor device, which is a step of diffusing and forming the same conductivity type surface diffusion region.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the high-concentration impurity region is of a first conductivity type, and the third step is a step of removing the first impurity from the inner wall of the trench. A gist of the present invention is a method of manufacturing a semiconductor device in which a conductive type impurity is diffused to form the side wall conductive region and a first conductive type diffusion region is also formed in the second conductive type diffusion region.

In the invention described in claim 5, in any one of claims 1 to 3, the second step includes a step of arranging a diffusion region of the first conductivity type in the diffusion region of the second conductivity type. It is intended to include.

According to a sixth aspect of the present invention, in any one of the first to fourth aspects, the semiconductor element formed in the island region is a bipolar transistor, and the high-concentration impurity region is a buried collector region thereof. The gist is that the second conductivity type diffusion region is a base region thereof.

[Operation] According to the first aspect of the present invention, in the first step, a semiconductor layer of the first conductivity type is disposed on the substrate via the high-concentration impurity region on the side facing the substrate. In the second step, a part of a semiconductor element is formed on the surface of the semiconductor layer of the first conductivity type, which is to be an island region later, with the semiconductor layer of the first conductivity type.
A second conductivity type diffusion region for forming a PN junction is formed, and thereafter, a trench is formed from the surface of the first conductivity type semiconductor layer to the substrate, and the semiconductor layer defines an island region for forming a semiconductor element. Form. In a third step, a sidewall conductive region electrically connected to the high-concentration impurity region in the island region is arranged along the inner wall of the trench from the high-concentration impurity region to the surface of the semiconductor layer. In a fourth step, an insulating layer is formed on the inner wall of the trench so as to surround the outer periphery of the island region.

According to the invention of claim 2, even if the third step is a step of diffusing an impurity of the same conductivity type as that of the high-concentration impurity region from an inner wall of the trench to form the sidewall conductive region, Is achieved.

According to the invention of claim 3, in the third step, the surface of the same conductivity type connected to the high-concentration impurity region and the sidewall conductive region is also formed on the surface of the first conductivity type semiconductor layer in the island region. The process can be shortened by diffusing the diffusion region.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the high-concentration impurity region is of the first conductivity type, and the third step includes the step of removing the first conductivity type impurity from the inner wall of the trench. Is diffused to form the side wall conductive region, and at the same time, the first conductive type diffusion region is formed in the second conductive type diffusion region, whereby the process can be shortened.

First Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device in which the bipolar transistor of this embodiment is integrated, and FIGS. 2 to 10 show the manufacturing steps.

First, as shown in FIG. 2, the surface of an N-type silicon substrate 10 is mirror-polished, and antimony is diffused using a gas phase diffusion method to form an N ⁺ region which becomes a part of a collector of a bipolar transistor having a thickness of 3 μm. Form 11. Also, the third
As shown in the figure, the surface of the P-type silicon substrate 12 is mirror-polished and thermally oxidized to form a 0.9 μm thick silicon oxide film 13 as an insulating layer. Then, as shown in FIG. 4, the two substrates 10 and 12 are bonded together so that the N ⁺ region 11 of the silicon substrate 10 and the silicon oxide film 13 of the P-type silicon substrate 12 face each other, and are heated to 1100 ° C. By the direct joining method.

Next, as shown in FIG. 5, unnecessary portions of the N-type silicon substrate 10 are removed by using a polishing method, and the thickness of the N-type silicon substrate 10 is reduced to 5 μm. As a result, a substrate corresponding to a conventional embedded epi-wafer is formed. In this method, since the substrate does not change depending on the type (product type) of the product as in the case of the buried epi, it is possible to stock this wafer and start the mask process from the base forming process.

The arrangement of the semiconductor layer having the N ⁺ region 11 which is a part of the collector of the bipolar transistor on the insulating layer on the surface of the substrate so far is the same as that of the silicon oxide film 13 in FIG. A glass substrate or a sapphire substrate may be used in place of the P-type silicon substrate 12, or a similar structure may be made by SIMOX (Separation by Implanted Oxygen). Alternatively, a P-type silicon substrate and a high-concentration N-type substrate are joined in a state where a silicon oxide layer is interposed therebetween, and unnecessary portions of the high-concentration N-type substrate are removed using a polishing method. A similar structure may be made by forming silicon.

Subsequently, as shown in FIG. 6, a P-type region 14 is formed on the N-type silicon substrate 10 by using a mask for forming a base and using a usual photoetching technique and a boron diffusion technique. Further, a silicon oxide film 15 is formed on the surface of the N-type silicon substrate 10 as a surface insulating film.

Then, as shown in FIG. 7, phosphorus etching is performed by photoetching using a mask for forming an emitter and vapor diffusion to form an N ⁺ region 16 serving as an emitter region and a collector region on the N-type silicon substrate 10.

Next, as shown in FIG. 8, the resist 17 is masked.
The silicon oxide film 15 around the transistor formation region is removed using an HF-based etchant, and further N 2 is added using a reactive ion etching apparatus using an SF _6- based etching gas.
The mold silicon substrate 10 is etched to form a trench 18 reaching the silicon oxide film 13 at the bonding interface. As a result, a transistor island is formed. Then, as shown in FIG. 9, a trench 18 is formed by vapor phase diffusion using POCl _3.
N ⁺ region 19 which becomes a part of the collector of the bipolar transistor is formed on the side wall of. At the same time, a silicon oxide film 20 as an insulating layer is formed on the side wall of the trench 18 at 0.7 μm.

Incidentally, the formation of the N ⁺ region 19 is not limited to the gas phase diffusion, but also to the trench 18.
Or forming an N ⁺ region 19 by ion implantation obliquely, may be formed N ⁺ region 19 by heat treatment by placing a PSG on the side wall of the trench 18 by the LPCVD method.

Next, as shown in FIG. 10, a polysilicon 21 is formed by LPCVD so as to fill the trench 18 with a hole. At this time, since the polysilicon 21 is also formed on the silicon oxide film 15 on the surface and irregularities are formed on the surface, the etching rate of the resist and the polysilicon is adjusted by using a dry etching method to perform the flattening process. Do. Thereafter, the surface of the polysilicon 21 is oxidized to form a silicon oxide film 22.

Subsequently, as shown in FIG. 1, after a contact hole is formed by an ordinary method, an aluminum wiring 23 is formed to form a bipolar IC. In this way, an IC in which bipolar transistors separated from each other are integrated can be obtained.

As described above, in the present embodiment, the N-type silicon substrate (the first conductive layer) is formed on the silicon oxide film 13 of the P-type silicon substrate 12 on the side facing the substrate 12 via the N ⁺ region (high-concentration impurity region) 11. (A first semiconductor layer) 10 (first step), and a silicon substrate 10
PN that forms part of a transistor (semiconductor element) with 10
A p-type region (diffusion region of second conductivity type) 14 for forming a junction is formed, and thereafter, from the surface of the N-type silicon substrate 10 to the P-type silicon substrate 12, an island region for transistor formation is formed in the N-type silicon substrate 10. Is formed (second step), and N ⁺ electrically connected to the N ⁺ region 11 in the island region is formed.
A region (sidewall conductive region) 19 is arranged from the N ⁺ region 11 to the surface of the N-type silicon substrate 10 along the inner wall of the trench 18 (third step) so as to surround the outer periphery of the island region. A silicon oxide film (insulating layer) 20 was formed on the inner wall of the trench 18 (fourth step).

As a result, the P-type silicon substrate 12 having the silicon oxide film 13 and the P-type silicon substrate 12
N ⁺ region (high concentration impurity region) 11 on the side facing the substrate 12
An N-type silicon substrate 10 having an N-type silicon substrate 10, a trench 18 which extends from the surface of the N-type silicon substrate 10 to the substrate 12 and partitions the N-type silicon substrate 10 to form an island region for forming a transistor (semiconductor element); A P-type region (second conductivity type diffusion region) 14 disposed on the surface of the island region of the silicon substrate 10 and forming a PN junction that forms part of a transistor with the N-type silicon substrate 10; disposed on the surface of the island region of the substrate 10, the N ⁺ region 11, the N ⁺ region (surface diffusion region) 16 of the same conductivity type is arranged along an inner wall of the trench 18, the N ⁺ region 11 N ⁺ region 19 connecting with N ⁺ region 16
A semiconductor device including (sidewall conductive region) and a silicon oxide film (insulating layer) 20 disposed on the inner wall of trench 18 so as to surround the outer periphery of the island region is formed.

Therefore, the lower surface is insulated and separated by the silicon oxide film 13 when the silicon oxide film 13 is bonded therebetween, and the side surface is insulated and separated by the silicon oxide film 20 on the side wall after the trench is formed. Without using the isolation region (P ⁺ region) 3 of this embodiment, an IC can be obtained in which bipolar transistors whose elements are separated by insulators on the entire periphery are integrated and can be miniaturized. After the trench is formed,
By performing gas phase diffusion using POCl ₃ , it is possible to surround the entire side surface of the transistor island with N ⁺ regions 11, 16, and 19 without adding a mask as compared with the junction isolation method shown in FIG. Is simplified, the saturation voltage Vsat of the bipolar transistor can be lowered, and the current capacity can be increased. In the conventional PN junction isolation method, the saturation voltage Vs is increased by adding one mask to form the deep N ⁺ region 4.
A bipolar transistor with a small at was formed.
Further, in the conventional PN junction isolation method, if an attempt is made to form a deep N ⁺ region 4 around the element in order to lower the saturation voltage Vsat, it is necessary to provide a gap between the isolation region (P ⁺ region) 3. However, without such a situation, N ⁺ region 19 can be arranged in contact with silicon oxide film 20.

Further, in the conventional bipolar IC using the PN junction isolation method, the deep N ⁺ region 4 is expanded in the lateral direction by ion implantation and subsequent annealing when the deep N ⁺ region 4 is formed, and its width is 5 to 6 μm. However, in this embodiment, since the diffusion from the side wall of the trench is used, the width of the N ⁺ region 19 can be reduced to 2 to 3 μm. Further, when the conventional PN junction isolation method performing heat treatment after formation of the buried N ⁺ region 1, but the buried N ⁺ region 1 had had spread, in the present embodiment miniaturization without such that It becomes possible.

In this manner, as is apparent from a comparison between FIG. 1 and FIG. 18, in the present embodiment, it is possible to configure only the active regions (base, emitter, and collector) of the transistor with less unnecessary portions.

Furthermore, the conventional PN junction isolation method has a drawback in that a breakdown caused by punch-through between the isolation region 3 and the base and a reach-through caused between the isolation and the collector occur.
This embodiment does not have the disadvantage. Furthermore, although a parasitic MOS transistor is formed between the base region and the isolation region 3 in the conventional insulation separation method, this embodiment does not have the drawback.

Further, when the IGBT or DMOS is integrated using the P-type silicon substrate 12, the potential of the collector of the bipolar transistor is fixed, so that it is prevented from being adversely affected by the substrate potential of the IGBT or DMOS. .

Further, it becomes a mask for forming a base of the first mask, so that a conventional mask for burying epi formation by the PN junction separation method can be eliminated. In addition, the wafers having the laminated structure of the N-type silicon substrate 10 / N ⁺ silicon 11 / silicon oxide film 13 / silicon substrate 12 by lamination shown in FIG. 5 do not depend on the type (product type) of the product. You can stock. in this way,
Since a mask for forming a buried layer is not required, and the substrate can be stocked, the manufacturing period can be shortened.

Furthermore, in this embodiment it is possible to surround the whole of the transistors Island N ⁺ regions 11,16,19, can be the N ⁺ regions 11,16,19 and shield layer.

Second Embodiment Next, a second embodiment will be described.

In this embodiment, as shown in FIG. 6 in the first embodiment, after forming the base region, a bipolar IC is manufactured as shown in FIGS.

First, as shown in FIG. 11, a silicon nitride film 24 is formed on the entire surface of an N-type silicon substrate 10 by using the LPCVD method, and a silicon nitride film of an emitter formation region A1, a collector / trench formation region A2, and a trench formation region A3 is formed. 24 is removed using a photoetch technique. Then, as shown in FIG. 12, a resist 25 is arranged on the N-type silicon substrate 10 except for the trench formation portion by a photolithography process. Further, as shown in FIG. 13, a trench 26 is formed, and thereafter, the resist 25 is removed. Subsequently, using the silicon nitride film 24 as a mask, the silicon oxide film 15 in the emitter and collector formation region is removed.

Next, as shown in FIG. 14, the emitter diffusion and the side wall diffusion of the trench 26 are performed by vapor phase diffusion using POCl ₃ to form an N ⁺ type region 27 which becomes a part of the collector. A silicon oxide film 28 is formed. Then, as shown in FIG. 15, after the hole is filled with the polysilicon 29 and the surface silicon oxide film 30 is formed, the contact and the aluminum wiring 31 are formed.

As a result, an IC in which the bipolar transistors separated from each other are integrated is manufactured.

According to this embodiment, the number of steps can be reduced because the emitter diffusion and the side wall N ⁺ diffusion are performed simultaneously.

The present invention is not limited to the first and second embodiments, but may be applied to, for example, an IC including a digital element such as BiCMOS. Further, in an IC in which various active elements and passive elements are integrated, it may be used when it is desired to surround the island of the bipolar transistor with an insulator.

Further, as shown in FIG. 16, a lateral PNP transistor 35 and a lateral NPN transistor 36 may be integrated. That is, the insulating film 32 has an N ⁻ region 33 on its bottom surface.
The N ^- silicon substrate 34 is arranged as an island of the PNP transistor 35, an island made of a P ^- type semiconductor of the NPN transistor 36 is formed on the insulating film 32, and an N ⁺ region 37 is formed on one side of the island of the PNP transistor 35. Then, an emitter region 38, a collector region 39, and a silicon oxide film 44 are formed. On the other hand, NP
After forming an N ⁺ emitter region 40 and a collector region 41 on the island of the N transistor 36 and forming a P ⁻ diffusion region 42, a P ⁺ base region 43 is formed.

Further, as shown in FIG. 17, the structure may be such that the silicon oxide film 13 in FIG. 1 is eliminated.

Further, a conductive material such as silicide may be used instead of the N ⁺ region 19 in FIG. 1 to electrically connect the N ⁺ region 11 and the N ⁺ region 16. Further, the N ⁺ regions 16 and 19 may be electrically connected by using a conductive material instead of the N ⁺ region 11 in FIG.

Further, on the state (N-type silicon substrate 10 shown in FIG. 2 N ⁺
From the state where the region 11 is formed), an annular groove is formed on the surface of the N-type silicon substrate 10 and the P-type silicon substrate 12 having the silicon oxide film 13 on the surface is joined. May be polished to separate transistor islands.

Further, the N ⁺ region 19 which is a part of the collector of the bipolar transistor does not need to be formed on the entire circumference of the island, and may be provided on, for example, three sides of a rectangular transistor island and not on the other side. Good.

[Effects of the Invention] As described in detail above, according to the first to sixth aspects of the present invention, there is no need for a mask for forming a high-concentration impurity region required in a conventional PN isolation element. The cost can be reduced, and the manufacturing can be easily performed.

Also, in the conventional example, at the time of ion implantation from the substrate surface direction,
During the subsequent annealing, the deep N ⁺ region partly spreads in the lateral direction, so that the area occupied by the element was increased. However, in the present invention, the side wall conductive region was raised along the inner wall of the trench. Since it can be arranged from the concentration impurity region to the surface of the semiconductor layer, it does not spread laterally from the side wall conductive region, does not increase the occupied area of the element, and can be miniaturized.

[Brief description of the drawings]

1 to 10 show a first embodiment, FIG. 1 is a cross-sectional view of a bipolar IC, FIG. 2 shows a manufacturing process, FIG. 3 shows a manufacturing process, and FIG. FIG. 5 shows a manufacturing process, FIG. 5 shows a manufacturing process, FIG. 6 shows a manufacturing process, and FIG.
FIG. 8 shows a manufacturing process, FIG. 8 shows a manufacturing process, FIG. 9 shows a manufacturing process, FIG. 10 shows a manufacturing process,
11 to 15 show a second embodiment, FIG. 11 shows a manufacturing process, FIG. 12 shows a manufacturing process, FIG. 13 shows a manufacturing process, and FIG. 14 shows a manufacturing process. FIG. 15 shows a process, FIG. 15 shows a manufacturing process, FIG. 16 shows a bipolar IC showing another example, FIG. 17 shows a bipolar IC showing another another example, FIG. Is a diagram showing a conventional bipolar IC. 10 is an N-type silicon substrate, 11 is an N ⁺ region, 18 is a trench, 19
Is an N ⁺ region, 20 is a silicon oxide film as an insulating layer, and 27 is an N ⁺ region as an emitter region.

Claims (6)

(57) [Claims] 1. A first step of disposing a semiconductor layer of a first conductivity type on a substrate via a high-concentration impurity region on a side facing the substrate; and, in the semiconductor layer of the first conductivity type, an island later A second conductivity type diffusion region forming a PN junction that forms a part of a semiconductor element with the first conductivity type semiconductor layer is formed on a surface to be a region, and thereafter, the first conductivity type semiconductor layer surface A second step of forming a trench for partitioning an island region for forming a semiconductor element in the semiconductor layer, and a sidewall conductive region electrically connected to the high-concentration impurity region in the island region. A third step of arranging from the high concentration impurity region to the surface of the semiconductor layer along the inner wall of the trench; and forming an insulating layer on the inner wall of the trench so as to cover the outer periphery of the island region. A fourth step, comprising: The method of manufacturing a semiconductor device according to symptoms. 2. The method according to claim 1, wherein the third step is a step of diffusing an impurity of the same conductivity type as that of the high-concentration impurity region from an inner wall of the trench to form the sidewall conductive region. 13. The method for manufacturing a semiconductor device according to item 5. 3. The third conductive type surface diffusion region connected to the high-concentration impurity region and the sidewall conductive region also on the surface of the first conductive type semiconductor layer in the island region. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a diffusion layer. 4. The high-concentration impurity region is of a first conductivity type. In the third step, the first conductivity type impurity is diffused from an inner wall of the trench to form the sidewall conductive region, and 4. The method according to claim 1, further comprising forming a first conductivity type diffusion region in the two conductivity type diffusion region. 5. 5. The method according to claim 1, wherein the second step includes a step of arranging a first conductivity type diffusion region in the second conductivity type diffusion region. 13. The method for manufacturing a semiconductor device according to item 5. 6. The semiconductor device formed in the island region is a bipolar transistor, the high-concentration impurity region is a buried collector region thereof, and the second conductivity type diffusion region is a base region thereof. The method for manufacturing a semiconductor device according to claim 1.