JPS60136327A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of masks to be used while simplifying the procedure, by forming field oxide films of an isolating oxide film between a collector outlet and a base region and of an inactive region at the same time with the formation of an oxide film in an isolating U groove. CONSTITUTION:A channel stopper layer 8 is formed within each of U grooves 7a and 7b. An insulation film 9, an oxide film for example, is then formed within each of the U grooves 7a and 7b through heat oxidation. In the next step, polysilicon is deposited in a relatively large thickness so that the U grooves 7a and 7b are filled with the polysilicon 12. After a nitride film 5 and an oxide film 4 are removed by photo etching from the part where an isolation region is formed, heat oxidation is performed with the use of the residual nitride film as a mask, whereby an oxide film 13 is formed while, at the same time, a field oxide film 6 is formed on the surface of the inactive region and an isolating oxide film 10 is also formed in an intermediate part between the base region and the region to be a collector outlet.

Description

[Detailed Description of the Invention] [Field of Application] The present invention relates to a technology that is effective when applied to semiconductor technology and the process of semiconductor devices, for example, for the formation of an isolation oxide film formed on the main surface of a semiconductor substrate. Concerning techniques that can be used effectively.

[Background technology] Currently, as a method for separating elements in semiconductor integrated circuits,
A junction isolation method using a diffusion layer and an oxide film isolation method using a selective oxide film called LOGO8 on the surface of a substrate are being carried out. However, in these isolation methods, the width of the element isolation region is made relatively large, and as elements become smaller, the ratio occupied by the element isolation region increases.
This becomes an obstacle to increasing the density of I (large-scale integrated circuits).

Therefore, the present applicant cut away the portion that would become the element isolation region to form a U-shaped groove (hereinafter referred to as the U-groove), formed an insulating film inside the U-groove, and then cut the inside of the U-groove. Polysilicon (
He proposed an isolation technology called the U-groove isolation method, in which device isolation regions are filled with polycrystalline silicon.
7-168355).

In the invention of the prior application, as shown in FIG.
7a and 27b, and a shallow U-groove isolation region 27c that penetrates only the epitaxial layer 3 and reaches the surface of the buried layer 2 is used to separate the diffusion layer 14 serving as a collector outlet and the base diffusion M16. Let's do it. Alternatively, as shown in FIG. 2, a U-groove isolation region 27a with deep isolation between elements may be used.

27b, and is separated from the collector outlet 14 by a relatively thick oxide film 10.

However, the deep U-groove isolation regions 27a, 27 as described above
In the isolation structure using the shallow U-groove isolation region 27c, it is necessary to form LOCO3, a deep U-groove, and a shallow U-groove, which requires three masks and complicates the process. In addition, in the U-groove separation method, since it is difficult to control the depth of the U-groove, there is a risk that the U-groove 27c becomes too deep.
There is a disadvantage that the collector resistance increases and the operating speed of the transistor decreases.

On the other hand, in a structure in which the oxide film 10 is used to separate the collector outlet 14 and the base diffusion layer 16, the oxide film 10
Providing a separate process for forming 0 would complicate the process. Therefore, it is conceivable to form the isolation oxide film 10 at the same time as a thick field oxide film formed using 1-4 acos or isoplanar technology, which is formed in an inactive area around the chip, for example.

However, when the isolation oxide film 10 is formed by such a method, bird's beaks are formed at both ends of the oxide film 10 as shown in FIG. Then, since the oxide film is thick, U
There is a possibility that the trench will not be able to be dug. Also, if an isolation oxide film is formed a little inside the U-groove isolation region, the oxide film 1o
The oxide film 10 becomes thinner at the boundaries between both ends of the U-groove isolation regions 27d and 27e. As a result, the sign A
It has been found that there is an inconvenience in that the collector drawer 1'' 14 and the base diffusion layer are short-circuited and cannot be sufficiently separated at the location shown in FIG.

Furthermore, since the inactive region is mainly used as a wiring region, the oxide film formed in the inactive region at the chip periphery must be formed to be relatively thick in order to reduce the wiring capacitance.

[Objective of the Invention] An object of the present invention is to reduce the number of masks used in the process and improve device characteristics when applied to the process of a semiconductor device in which elements are separated by a U-groove isolation region, for example. An object of the present invention is to provide a method for manufacturing a semiconductor device that can simplify the process without causing deterioration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention has the following advantages: 1. For example, in the process of a bipolar integrated circuit in which device isolation is performed by a U-groove isolation region, at the same time as the oxide film is formed in the U-groove for isolation, the collector lead-out port and By forming the isolation oxide film between the base region and the field oxide film in the inactive region, there is no need to provide separate steps for forming the isolation oxide film and the field oxide film. This achieves the above objectives of simplifying the process without reducing the number of masks used.

The present invention will be described in detail below along with examples.

[Embodiment] FIGS. 4 to 9 show an embodiment in which the present invention is applied to a bipolar integrated circuit in the order of manufacturing steps.

In this embodiment, although not particularly limited, an oxide film is formed on a semiconductor substrate 1 made of P-type silicon, and holes for buried diffusion patterns are formed at appropriate positions in the oxide film.
Using this oxide film as a mask, N type impurities are thermally diffused to partially form an N+ buried layer 2. After removing the oxide film, an N-type epitaxial layer 3 is grown on it by a vapor phase growth method, and an oxide film (Si02 film) 4 and a nitride film (Si3N4 film) 5 are formed on the surface of the N-type epitaxial layer 3. Figure 4).

Next, the nitride film 5 and oxide film 4 in the portion where the U-groove isolation region is to be formed (around the bipolar L-transistor) are removed by etching, and then hydrazine etching is performed to form a taper at the entrance of the trench. Thereafter, dry etching is performed to form relatively deep U-grooves 7a and 7b that reach the P-type substrate 1, resulting in the state shown in FIG.

Next, the U groove 7a formed as described above.

A channel stopper layer 8 is formed by implanting ions of boron or the like into 7b and performing heat treatment. Thereafter, an insulating film 9 such as an oxide film is formed inside the U grooves 7a and 7b by thermal oxidation. Then cover the entire board with polysilicon (
Polycrystalline silicon) is deposited 41 times thicker using the CVD method (chemical vapor deposition method),
U groove 7a.

7b is filled with polysilicon. Then, the polysilicon layer on the surface of the substrate is removed and planarized by dry etching, so that polysilicon 12 remains in the U grooves 7a and 7b (FIG. 6).

Then, thermal oxidation is performed to remove the polysilicon 12 inside the U-groove.
The surface of the polysilicon 12 is oxidized to form an oxide film 1 on the second surface of the polysilicon 12.
3, but in this example, before forming the oxide film 13 on the polysilicon 12, an inactive area at the periphery of the chip that will be the wiring area, and an area between the base area and the collector extraction port are formed. After removing the nitride film 5 and oxide film 4 on the surface of the portion where the isolation region is to be formed by photoetching,
Thermal oxidation is performed using the nitride film 5 as a mask.

Then, as shown in FIG. 7, an oxide film 13 is formed on the surface of the polysilicon 12, and at the same time, a field oxide film 6 is formed on the surface of the inactive region, and a region that will become the base region and the collector outlet is formed. An isolation oxide film 10 is formed in the middle portion between the two. In this case, each of the oxide films 6
, 10.16 can be formed to a thickness of approximately 60 mm or more.

Next, the nitride film 5 above the collector lead-out port is removed, and N-type impurity ions are implanted and thermally diffused to form an N-type diffusion layer 14 that will become the collector lead-out port. after that,
After the nitride film 5 is completely removed, P-type impurity ions are implanted to form a base region over the entire main surface of the substrate. Then, nitride film 15 is again formed on the oxide films 4 and 6, and then heat treatment is performed to form a base diffusion layer 16, and then the nitride film 15 in the portion that will become the emitter region is removed.

After that, the oxide film 4 on the surface of the part that will become the emitter region is
is removed by etching, and then C is applied to the entire nitride film 15.
A thin layer of polysilicon is deposited using the VD method.

Then, ions of an N-type pure substance such as arsenic are implanted into this polysilicon layer, and then heat treatment is performed to form an emitter diffusion layer 18 by diffusion from the polysilicon layer. Next, the polysilicon layer is photo-etched to remove unnecessary portions, leaving a polysilicon electrode 19 on the emitter diffusion layer 18, as shown in FIG.

In the above case, the emitter diffusion layer 18 is formed by diffusion from the polysilicon layer, but ion implantation and heat treatment for forming the emitter are performed before the polysilicon deposition. The emitter may be formed by performing ion implantation and diffusion twice before and after the position.

After forming the emitter diffusion layer 18, an interlayer insulating film 2 such as a PSG film (phosphorus silicate glass film) is formed on the nitride film 15.
0 is formed by CVD method. Then, etching is performed using a photoresist as a mask to form contact holes 1 to 21a of each electrode portion of the base, emitter, and collector.
~21c is formed.

After that, a wiring material such as aluminum is deposited on the entire surface of the substrate, and then aluminum electrodes 22a to 22 are formed by etching the holes 1 to 2.
2c and aluminum wiring are formed, and a final passivation film 23 such as a 5i02 film is formed thereon to obtain a completed state as shown in FIG.

In the above embodiment, at the same time as the oxide film 13 is formed on the surface of the polysilicon 12 in the U-groove isolation region, the field oxide film 6 in the inactive region, the diffusion layer 14 serving as the collector extraction port, and the base diffusion layer 16 are formed. Isolation oxide film 10 between
Therefore, the steps for forming the field oxide film 6 and the isolation oxide film 10 are unnecessary. Moreover, unlike the case where the collector outlet 14 and the base diffusion layer 16 are separated from each other by a shallow U-groove, there is no need to cut the U-groove twice, and the deep LJ
ζ7a and 7b can be formed at once. Therefore, the process becomes simple r1i.

Further, the field oxide film 6 is formed by LOGO8, and the isolation between elements is formed by a deep U groove and a shallow LJ i+1.
If this is done, three masks are required: a mask for forming LOGO8, a second mask for forming the deep U-groove, and a mask for forming the shallow U-groove. Furthermore, even if the isolation region between the base and collector is an oxide film, this isolation oxide film (10) and the field oxide film (10)
If these are formed in separate steps, three masks will still be required, including the mask for forming the U-groove.

However, in the above embodiment, since the isolation between the base and collector is done by an oxide film and is formed at the same time as the field oxide film 6, even if the mask for forming the U-groove is included, only 2
Only one sheet will be enough. Therefore, it is possible to save time and cost for creating a mask, and it is possible to reduce costs.

Moreover, tb formed by a process like the above example
In the bipolar transistor, the isolation oxide 11i10 between the collector outlet 14 and the base diffusion layer 16 is
The thickness is approximately uniform from the center to both ends. Therefore, if the isolation oxide film 1O is formed at the same time as the field oxide film by LOGO3 or isoplanar (the third
As shown in the figure, U-groove isolation regions 27 at both ends of the oxide film 10
d, 27e will not become thinner and the distance between the base and collector will not be shortened, and the base and collector will be sufficiently insulated. Also, the thickness of the oxide film 10 can be controlled. Since this is better than the depth controllability of the U-groove isolation region, variations in the characteristics of the 1-transistor are reduced, and the U-groove isolation region separates the collector outlet 14 from the base diffusion WJ 16. There is no fear that the collector resistance will increase due to [J if'i' penetrating the epitaxial layer 2 and reaching the buried layer 3 as in the case of [J if'i']. As a result, 1~
The characteristics of transistors will be improved.

In the above embodiment, the field oxide film 6 and the isolation oxide film 10 provided in the inactive region are
Although they are formed simultaneously with the oxide film 13 on the surface of the isolation region, only either the isolation oxide film 10 or the field oxide film 6 may be formed simultaneously with the oxide film 13 on the surface of the U-groove isolation region.

For example, the field oxide film 6 in the inactive region may be formed using the same LOGO 8 as in the prior art, and only the isolation oxide film IO may be formed at the same time as the oxide film 13 on the surface of the U-groove isolation region.

Further, in the above embodiment, the emitter region is formed by diffusion from the polysilicon electrode 19 formed thereon, but the emitter region is formed by diffusion from the polysilicon electrode 19 formed thereon.
The emitter diffusion layer 18 may be formed by ion implantation of N-type impurities directly onto the main surface of the substrate.

Furthermore, in the above embodiment, the N-type diffusion layer 14 serving as the collector outlet is formed before the base and emitter regions are formed, but the collector outlet may be formed after the base and emitter are formed. good.

Furthermore, in the above embodiment, the field oxide film 6 in the inactive region and the isolation oxide film 10 between the base and collector are
Oxide film 13 on the surface of polysilicon 12 in the U-groove isolation region
Although the field oxide film 6 and the isolation oxide film 10 may be formed simultaneously with the formation of the oxide film 9 formed inside the U-groove.

[Effect] In the process of bipolar integrated circuits in which device isolation is performed by the U-groove ttlt region, an oxide film is formed on the polysilicon surface in the isolation U-groove and the collector lead-out port and base region are Since the oxide film for separate books and the field oxide film in the inactive area are formed between the two, there is no need to provide separate processes for forming the oxide film for separate books and the field oxide film. This has the effect of simplifying the process and reducing the number of required masks, thereby reducing loss.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the insulating film inside the U-groove is composed of only an oxide film, but it may also have a two-layer structure in which a nitride film is formed inside the oxide film, or an oxide film is further formed inside the nitride film. It may be three-layered.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to bipolar integrated circuits, which is the field of application that formed the background of the invention, but the invention is not limited to this. It can generally be used in semiconductor devices that require an oxide film on the main surface of a semiconductor substrate.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a configuration example of a bipolar transistor in a semiconductor device of a prior application to which the U-groove isolation method is applied, and FIG. 2 is a sectional view showing another configuration example. FIG. 3 is a sectional view taken along the at-to line in FIG. 2, and FIGS. 4 to 9 are sectional views showing an embodiment of the present invention in the order of manufacturing steps. 1... Semiconductor substrate, 2... N0 buried layer, 3...
...Epitaxial layer, 4...Oxide film, 5,15.
...Nitride film, 6...Field oxide film, 7a, 7
b...il+W (U groove), 8...channel stopper layer, 9...insulating film (In film), 1 discharge...
Isolation insulating film (isolation oxide film), 11... Insulating film (
nitride film), 12...dielectric (polysilicon), 13
... Oxidation 1 model, I4... Diffusion layer serving as collector outlet, 16... Diffusion layer for base, 18...
Emitter diffusion layer, 19... self-polysilicon electrode, 20
...717 insulating film (PSG film), 21a-21c
""Contact 1-Ball, 22a-22c...
Aluminum electrode, 23...passivation film, 27a
~27e...U groove isolation region. Figure 1 Figure 2 Figure 4 Continuation of Figure 1 page 0 Inventor Katsumi Ogiue Inside Center 1, Kamimizuki-cho, Kodaira City

Claims (1)

[Claims] 1. tR is dug between the active regions of the elements formed on the main surface of the semiconductor substrate, an insulating film layer is formed inside, and then a dielectric is filled, and the surface of the dielectric is heated. In a method of manufacturing a semiconductor device in which an isolation region is formed by forming an oxide film, at least between a diffusion layer serving as a collector outlet and a base diffusion layer of a bipolar transistor formed on the main surface of a semiconductor substrate. A semiconductor device characterized in that an isolation oxide film to be formed or a field oxide film to be formed in an inactive region is formed at the same time as an oxide film to be formed on a dielectric surface constituting the isolation region. manufacturing method. 2. Claim 1 characterized in that the isolation oxide film and the field oxide film formed on the main surface of the semiconductor substrate are formed at the same time as the oxide film formed on the dielectric surface. A method for manufacturing a semiconductor device according to section 1.