JPS6310896B2 - - Google Patents
Info
- Publication number
- JPS6310896B2 JPS6310896B2 JP557380A JP557380A JPS6310896B2 JP S6310896 B2 JPS6310896 B2 JP S6310896B2 JP 557380 A JP557380 A JP 557380A JP 557380 A JP557380 A JP 557380A JP S6310896 B2 JPS6310896 B2 JP S6310896B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- silicon dioxide
- mask
- dioxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 94
- 235000012239 silicon dioxide Nutrition 0.000 claims description 47
- 239000000377 silicon dioxide Substances 0.000 claims description 47
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 31
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 238000005260 corrosion Methods 0.000 claims description 16
- 230000007797 corrosion Effects 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 241000293849 Cordylanthus Species 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- XUIMIQQOPSSXEZ-RNFDNDRNSA-N silicon-32 atom Chemical compound [32Si] XUIMIQQOPSSXEZ-RNFDNDRNSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特にその素子
分離構造の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an element isolation structure thereof.
第１図は、従来知られているシリコン基板と窒
化珪素膜との酸化膜の成長速度差を利用した選択
酸化法による素子分離構造の製造方法を示したも
のである。 FIG. 1 shows a conventionally known method for manufacturing an element isolation structure using a selective oxidation method that takes advantage of the difference in growth rate of an oxide film between a silicon substrate and a silicon nitride film.
第１図ａはシリコン結晶１１表面に熱酸化法に
より二酸化珪素膜１２を形成し、その上に窒化珪
素膜１３を形成し、さらに熱酸化法により窒化珪
素膜１３上に二酸化珪素膜１４を形成した後、素
子領域の形状を有するレジスト１５を形成した状
態を示す。 In FIG. 1a, a silicon dioxide film 12 is formed on the surface of a silicon crystal 11 by a thermal oxidation method, a silicon nitride film 13 is formed thereon, and a silicon dioxide film 14 is further formed on the silicon nitride film 13 by a thermal oxidation method. After that, a resist 15 having the shape of the element region is formed.
第１図ｂはレジスト１５を耐腐蝕マスクとし
て、二酸化珪素膜１４を腐蝕除去して、素子領域
の形状を有する二酸化珪素膜１４′を形成した後、
レジスト１５を除去した状態を示す。 FIG. 1b shows that after the silicon dioxide film 14 is etched away using the resist 15 as a corrosion-resistant mask to form a silicon dioxide film 14' having the shape of the device region.
A state in which the resist 15 has been removed is shown.
第１図ｃは二酸化珪素膜１４′を耐腐蝕マスク
として窒化珪素膜１３を腐蝕除去し、素子領域状
を有する窒化珪素膜１３′を形成した後、この窒
化珪素膜１３′を耐拡散マスクとして、非素子領
域に基板と同一導電型の不純物１６を拡散した状
態を示す。 In FIG. 1c, the silicon nitride film 13 is etched away using the silicon dioxide film 14' as a corrosion-resistant mask to form a silicon nitride film 13' having an element region shape, and then this silicon nitride film 13' is used as a diffusion-resistant mask. , which shows a state in which an impurity 16 of the same conductivity type as the substrate is diffused into a non-element region.
第１図ｄは窒化珪素膜１３′を耐酸化マスクと
して熱酸化を行い、非素子領域に厚い二酸化珪素
膜１７を形成することにより素子分離を行なつた
状態を示すものである。 FIG. 1d shows a state in which elements are isolated by performing thermal oxidation using a silicon nitride film 13' as an oxidation-resistant mask and forming a thick silicon dioxide film 17 in non-element regions.
しかしながら、従来のこの選択酸化法による素
子分離構造の製造方法は、非素子領域上に厚い二
酸化珪素膜を形成する際に所謂バーズビークが生
じて素子領域幅を狭めるという欠点を有してい
る。 However, the conventional manufacturing method of an element isolation structure using this selective oxidation method has a drawback that when a thick silicon dioxide film is formed on a non-element region, a so-called bird's beak occurs, which narrows the width of the element region.
素子の集積化が進んでいる現在、素子寸法は微
細化の一途たどつている。このような中で、前述
したような選択酸化による素子分離工程における
素子領域幅の狭ばまりは大きな問題である。つま
りバーズビーク量を初めから考えて、このくい込
み分をマスク寸法に入れておかなければならずこ
のことが大容量の集積回路を製造する場合にはチ
ツプ寸法に大きな影響を及ぼすことになる。 At present, as elements become more integrated, element dimensions continue to become smaller. Under these circumstances, the narrowing of the device region width in the device isolation process using selective oxidation as described above is a major problem. In other words, the amount of bird's beak must be considered from the beginning and this amount of penetration must be included in the mask dimensions, and this has a large effect on the chip dimensions when manufacturing large-capacity integrated circuits.
本発明は、非素子領域に素子分離のための熱酸
化膜を成長させる際に生じる素子領域への酸化膜
のくい込み、所謂バーズビークを防ぎ素子領域幅
の狭まりをなくすことにより高集積化に適した半
導体素子における素子分離構造の製造方法を提供
することを目的としている。 The present invention is suitable for high integration by preventing the so-called bird's beak, which is the penetration of the oxide film into the element region that occurs when a thermal oxide film is grown for element isolation in non-element regions, and eliminating narrowing of the element region width. It is an object of the present invention to provide a method for manufacturing an element isolation structure in a semiconductor element.
本発明によれば半導体結晶基板表面に二酸化珪
素膜を形成する工程、該二酸化珪素膜上に窒化珪
素膜を被着する工程、該窒化珪素膜上に素子領域
形状を有するマスク被膜を形成する工程、該マス
ク被膜を耐エツチングマスクとして非素子領域に
位置する前記窒化珪素膜、前記二酸化珪素膜およ
び前記基板表層部をエツチング除去する工程、前
記マスク被膜を除去する工程、残留した前記窒化
珪素膜を耐イオン注入マスクとして被素子領域に
前記基板と同一導電型不純物をイオン注入する工
程、多結晶シリコンを全面に被着する工程、該多
結晶シリコン表面に二酸化珪素膜を形成する工
程、該二酸化珪素膜上に非素子領域の形状を有す
るマスク被膜を形成する工程、該マスク被膜を耐
腐蝕マスクとして該二酸化珪素膜を腐蝕除去する
工程、該マスク被膜を除去する工程、こうして形
成した非素子領域の形状を有する二酸化珪素膜を
耐腐蝕マスクとして前記多結晶シリコンを腐蝕除
去する工程、こうして非素子領域に位置すること
となつた多結晶シリコンおよび素子領域における
窒化珪素膜を耐腐蝕マスクとして非素子領域の形
状を有する二酸化珪素膜を腐蝕除去する工程、前
記素子領域の形状を有する窒化珪素膜を耐酸化マ
スクとして前工程を経てなお非素子領域に残留し
ている多結晶シリコンを完全に酸化する工程、を
含むことを特徴とする半導体装置における素子分
離構造の製造方法を得る。 According to the present invention, a step of forming a silicon dioxide film on the surface of a semiconductor crystal substrate, a step of depositing a silicon nitride film on the silicon dioxide film, and a step of forming a mask film having an element region shape on the silicon nitride film. , a step of etching away the silicon nitride film, the silicon dioxide film, and the substrate surface layer located in the non-element region using the mask film as an etching-resistant mask; a step of removing the mask film; and a step of removing the remaining silicon nitride film. A step of ion-implanting impurities of the same conductivity type as the substrate into the device region as an ion implantation-resistant mask, a step of depositing polycrystalline silicon on the entire surface, a step of forming a silicon dioxide film on the surface of the polycrystalline silicon, and a step of forming a silicon dioxide film on the surface of the polycrystalline silicon. A step of forming a mask film having the shape of a non-device region on the film, a step of etching away the silicon dioxide film using the mask film as a corrosion-resistant mask, a step of removing the mask film, and a step of removing the mask film in the shape of the non-device region thus formed. A step of etching away the polycrystalline silicon using a shaped silicon dioxide film as a corrosion-resistant mask, and removing the polycrystalline silicon now located in the non-device region and a silicon nitride film in the device region as a corrosion-resistant mask. a step of etching away the silicon dioxide film having the shape of the device region, and a step of completely oxidizing the polycrystalline silicon remaining in the non-device region after the previous process using the silicon nitride film having the shape of the device region as an oxidation-resistant mask. A method for manufacturing an element isolation structure in a semiconductor device is provided, the method comprising:
以下本発明の典型的な一実施例及び本発明を絶
縁ゲート電界効果トランジスタと拡散層配線に応
用した例について第２図、第３図を用いて詳述す
る。 Hereinafter, a typical embodiment of the present invention and an example in which the present invention is applied to an insulated gate field effect transistor and a diffusion layer wiring will be described in detail with reference to FIGS. 2 and 3.
第２図ａは、第１導電型の半導体結晶基板とし
てｐ型シリコン結晶基板２１を用いその表面に熱
酸化法により二酸化珪素膜２２を形成し、さらに
その表面に化学蒸着法により窒化珪素膜２３を形
成してその上に素子領域の形状を有するレジスト
２５を形成した状態である。 In FIG. 2a, a p-type silicon crystal substrate 21 is used as a semiconductor crystal substrate of the first conductivity type, a silicon dioxide film 22 is formed on its surface by a thermal oxidation method, and a silicon nitride film 23 is further formed on its surface by a chemical vapor deposition method. This is a state in which a resist 25 having the shape of an element region is formed thereon.
第２図ｂは、前記レジスト２５を耐エツチング
マスクとして非素子領域の窒化珪素膜、二酸化珪
素膜及び基板シリコン表層部をスパツタエツチン
グ等々の手法でエツチング除去した状態である。 FIG. 2B shows a state in which the silicon nitride film, silicon dioxide film, and substrate silicon surface layer in the non-element region are etched away by sputter etching or the like using the resist 25 as an etching-resistant mask.
第２図ｃは、前記レジスト２５を除去した後、
素子領域の形状を有する窒化珪素膜２３′を耐イ
オン注入マスクとして、非素子領域に基板と同じ
第１導電型不純物として硼素をイオン注入して硼
素イオン注入層２６を形成した状態である。 FIG. 2c shows that after removing the resist 25,
Using the silicon nitride film 23' having the shape of the device region as an ion implantation-resistant mask, boron ions are implanted into the non-device region as an impurity of the same first conductivity type as the substrate to form a boron ion-implanted layer 26.
第２図ｄは化学蒸着法により多結晶シリコン膜
２７を形成してから熱酸化法により多結晶シリコ
ン膜２７表面に薄い二酸化珪素膜２８を形成し、
更に非素子領域上をレジスト２９で覆つた状態で
ある。 In FIG. 2d, a polycrystalline silicon film 27 is formed by chemical vapor deposition, and then a thin silicon dioxide film 28 is formed on the surface of the polycrystalline silicon film 27 by thermal oxidation.
Furthermore, the non-element region is covered with a resist 29.
第２図ｅは、レジスト２９を耐腐蝕マスクとし
て素子領域上に露出した二酸化珪素膜２８を腐蝕
除去し、レジスト２９を除去した後、非素子領域
の形状を有する二酸化珪素膜２８′および素子領
域上の窒化珪素膜２３′を耐腐蝕マスクとして多
結晶シリコン２７を腐蝕除去した状態である。こ
の製造工程における多結晶シリコン２７の腐蝕除
去は、多結晶シリコン面が窒化珪素膜２３′の表
面にくる程度に腐蝕除去して図示の状態に近くす
るが、あまりにも過度に腐蝕除去して多結晶シリ
コン面が窒化珪素膜２３′の下面下に来ないよう
にする。 FIG. 2e shows that the silicon dioxide film 28 exposed on the element region is etched away using the resist 29 as a corrosion-resistant mask, and after the resist 29 is removed, the silicon dioxide film 28' having the shape of a non-element region and the element region are removed. This is a state in which the polycrystalline silicon 27 has been removed by corrosion using the upper silicon nitride film 23' as a corrosion-resistant mask. In this manufacturing process, the polycrystalline silicon 27 is removed by corrosion to such an extent that the polycrystalline silicon surface comes to the surface of the silicon nitride film 23', resulting in a state similar to that shown in the figure. The crystalline silicon surface should not be below the lower surface of the silicon nitride film 23'.
第２図ｆは、非素子領域上の多結晶シリコン２
７′と素子領域上の窒化珪素膜２３′を耐腐蝕マス
クとして前記非素子領域上の薄い二酸化珪素膜２
８′を腐蝕除去した後、素子領域上の窒化珪素膜
２３′を耐酸化マスクとして非素子領域上の多結
晶シリコン２７′を熱酸化法により完全に酸化し、
厚い二酸化珪素膜２７ａを非素子領域に形成する
ことにより素子領域と非素子領域とを分離した状
態を示す。 Figure 2 f shows the polycrystalline silicon 2 on the non-element region.
7' and the silicon nitride film 23' on the element area as a corrosion-resistant mask, the thin silicon dioxide film 2 on the non-element area is
After etching away the polycrystalline silicon 27' on the non-element area using the silicon nitride film 23' on the element area as an oxidation-resistant mask, the polycrystalline silicon 27' on the non-element area is completely oxidized by thermal oxidation.
A state in which the element region and the non-element region are separated by forming a thick silicon dioxide film 27a in the non-element region is shown.
以上説明した本発明による素子分離法を実際の
半導体装置に応用した態様について、絶縁ゲート
電界効果トランジスタ及びそれに附属する拡散層
配線を例に、以下更に説明する。 A mode in which the element isolation method according to the present invention described above is applied to an actual semiconductor device will be further explained below, taking an insulated gate field effect transistor and its associated diffusion layer wiring as an example.
第３図ａは、第２図ｆで得た本発明による素子
分離構造を形成した後、素子領域上にある窒化珪
素膜２３′と二酸化珪素膜２２′を腐蝕除去し、熱
酸化法によりゲート酸化膜となる二酸化珪素膜３
１を形成し、さらに化学蒸着法により多結晶シリ
コン３２を成長させ、その上に熱酸化法により薄
い二酸化珪素膜３３を形成し、次に素子領域上に
ゲート電極の形状を有するレジスト３４を形成し
た状態である。 FIG. 3a shows that after forming the device isolation structure according to the present invention obtained in FIG. Silicon dioxide film 3 serving as an oxide film
1 is formed, polycrystalline silicon 32 is further grown by chemical vapor deposition, a thin silicon dioxide film 33 is formed thereon by thermal oxidation, and then a resist 34 having the shape of a gate electrode is formed on the element region. The situation is as follows.
第３図ｂは、前記レジスト３４を耐腐蝕マスク
として二酸化珪素膜３３を腐蝕除去し、ゲート電
極の形状を有する二酸化珪素膜３３′を形成して
から前記レジスト３４を除去し、次にこの二酸化
珪素膜３３′を耐腐蝕マスクとして多結晶シリコ
ン３２を腐蝕除去してゲート電極３２′を形成し
た状態である。 FIG. 3b shows that the silicon dioxide film 33 is etched away using the resist 34 as a corrosion-resistant mask to form a silicon dioxide film 33' having the shape of a gate electrode, and then the resist 34 is removed. This is a state in which the polycrystalline silicon 32 is removed by corrosion using the silicon film 33' as a corrosion-resistant mask to form a gate electrode 32'.
第３図ｃは、ゲート電極の多結晶シリコン３
２′を耐イオン注入マスクとしてゲート酸化膜３
１を通して第二導電型不純物として砒素又は燐を
イオン注入し、熱処理をして低抵抗ドレイン３
５、ソース３６および拡散層３７を形成し、図の
左側に絶縁ゲート電界効果トランジスタの、また
図の右側に拡散層配線の基本的断面構造が完成し
た状態を示す。 Figure 3c shows the polycrystalline silicon 3 of the gate electrode.
Gate oxide film 3 is formed using 2' as an ion implantation-resistant mask.
Arsenic or phosphorus is ion-implanted as a second conductivity type impurity through 1 and heat treated to form a low resistance drain 3.
5. The source 36 and the diffusion layer 37 are formed, and the basic cross-sectional structure of the insulated gate field effect transistor is shown on the left side of the figure, and the diffusion layer wiring is completed on the right side of the figure.
以上述べた通り本発明によれば、素子間分離構
造を形成する際にバーズビークが形成されないた
めにマスク寸法に近い素子領域が形成できるので
マスク寸法に余裕を見込む必要がなく、半導体装
置の高集積化に適した素子分離が行なえる。 As described above, according to the present invention, a bird's beak is not formed when forming an element isolation structure, so an element region close to the mask size can be formed, so there is no need to allow for a margin in the mask size, and it is possible to achieve high integration of semiconductor devices. It is possible to perform element isolation suitable for
さらに、実施例からもわかるように、非素子領
域におけるチヤンネルストツパとしての第１導電
型不純物と素子領域における第２導電型不純物と
の間に大きな段差があるため浮遊容量が小さくな
る。従つて本発明によつて素子分離すれば、結果
として高速化に適した半導体装置が得られる。 Furthermore, as can be seen from the examples, since there is a large step difference between the first conductivity type impurity as a channel stopper in the non-device region and the second conductivity type impurity in the device region, the stray capacitance is reduced. Therefore, if elements are separated according to the present invention, a semiconductor device suitable for high speed operation can be obtained as a result.
第１図ａ，ｂ，ｃ，ｄの各図は、従来知られて
いる選択酸化法を用いることによつて素子間分離
を行なつた製造プロセスの模式的断面図であり、
第２図ａ，ｂ，ｃ，ｄ，ｅ，ｆの各図は、本発明
の一実施例をプロセスを追つて示した模式的断面
図である。第３図ａ，ｂ，ｃは本発明によつて得
た第２図ｆの素子分離構造を出発点として、絶縁
ゲート電界効果トランジスタおよび拡散層配線を
製造するプロセスを説明する模式的断面図であ
る。
図において、各記号はそれぞれ次のものを示
す。１１：シリコン基板、１２：二酸化珪素膜、
１３：窒化珪素膜、１３′：素子領域の形状を有
する窒化珪素膜、１４：二酸化珪素膜、１４′：
素子領域形状を有する二酸化珪素膜、１５：素子
領域形状を有するレジスト、１６：チヤンネルス
トツパとしての不純物添加層、１７：二酸化珪素
膜、２１：シリコン基板、２２：二酸化珪素膜、
２３：窒化珪素膜、２５：素子領域形状を有する
レジスト、２２′：素子領域形状を有する二酸化
珪素膜、２３′：素子領域形状を有する窒化珪素
膜、２６：チヤンネルストツパとしての不純物添
加層、２７：多結晶シリコン、２８：二酸化珪素
膜、２９：非素子領域の形状を有するレジスト、
２７′：非素子領域の形状を有する多結晶シリコ
ン、２８′：非素子領域の形状を有する二酸化珪
素膜、２７ａ：二酸化珪素膜、３１：ゲート酸化
膜、３２：多結晶シリコン、３３：二酸化珪素
膜、３４：ゲート電極形状を有するレジスト、３
２′：ゲート電極、３３′：ゲート電極形状を有す
る二酸化珪素膜、３５：ドレイン領域、３６：ソ
ース領域、３７：不純物による配線層。
Figures 1a, b, c, and d are schematic cross-sectional views of a manufacturing process in which element isolation is achieved by using a conventionally known selective oxidation method.
Each of FIGS. 2a, b, c, d, e, and f is a schematic sectional view showing an embodiment of the present invention step by step. FIGS. 3a, b, and c are schematic cross-sectional views illustrating a process for manufacturing an insulated gate field effect transistor and a diffusion layer wiring starting from the element isolation structure of FIG. 2f obtained by the present invention. be. In the figure, each symbol indicates the following. 11: silicon substrate, 12: silicon dioxide film,
13: silicon nitride film, 13': silicon nitride film having the shape of an element region, 14: silicon dioxide film, 14':
silicon dioxide film having an element region shape, 15: resist having an element region shape, 16: impurity doped layer as a channel stopper, 17: silicon dioxide film, 21: silicon substrate, 22: silicon dioxide film,
23: silicon nitride film, 25: resist having element region shape, 22': silicon dioxide film having element region shape, 23': silicon nitride film having element region shape, 26: impurity doped layer as channel stopper, 27: Polycrystalline silicon, 28: Silicon dioxide film, 29: Resist having a shape of a non-element region,
27': polycrystalline silicon having a shape of a non-element region, 28': silicon dioxide film having a shape of a non-element region, 27a: silicon dioxide film, 31: gate oxide film, 32: polycrystalline silicon, 33: silicon dioxide Film, 34: Resist having gate electrode shape, 3
2': gate electrode, 33': silicon dioxide film having gate electrode shape, 35: drain region, 36: source region, 37: wiring layer made of impurities.
Claims (1)
する工程、該二酸化珪素膜上に窒化珪素膜を被着
する工程、該窒化珪素膜上に素子領域形状を有す
るマスク被膜を形成する工程、該マスク被膜を耐
エツチングマスクとして非素子領域に位置する前
記窒化珪素膜、前記二酸化珪素膜および前記基板
表層部をエツチング除去する工程、前記マスク被
膜を除去する工程、残留した前記窒化珪素膜を耐
イオン注入マスクとして被素子領域に前記基板と
同一導電型不純物をイオン注入する工程、多結晶
シリコンを全面に被着する工程、該多結晶シリコ
ン表面上に二酸化珪素膜を形成する工程、該二酸
化珪素膜上に非素子領域の形状を有するマスク被
膜を形成する工程、該マスク被膜を耐腐蝕マスク
として該二酸化珪素膜を腐蝕除去する工程、該マ
スク被膜を除去する工程、こうして形成した非素
子領域の形状を有する二酸化珪素膜を耐腐蝕マス
クとして前記多結晶シリコンを腐蝕除去する工
程、こうして非素子領域に位置することになつた
多結晶シリコンおよび素子領域における窒化珪素
膜を耐腐蝕マスクとして非素子領域の形状を有す
る二酸化珪素膜を腐蝕除去する工程、前記素子領
域の形状を有する窒化珪素膜を耐酸化マスクとし
て前工程を経てなお非素子領域に残留している多
結晶シリコンを完全に酸化する工程、を含むこと
を特徴とする半導体装置における素子分離構造の
製造方法。1. A step of forming a silicon dioxide film on the surface of a semiconductor crystal substrate, a step of depositing a silicon nitride film on the silicon dioxide film, a step of forming a mask film having an element region shape on the silicon nitride film, and the mask. A step of etching and removing the silicon nitride film, the silicon dioxide film, and the surface layer of the substrate located in the non-element region using the film as an etching-resistant mask, a step of removing the mask film, and a step of removing the remaining silicon nitride film by ion implantation. A step of ion-implanting impurities of the same conductivity type as the substrate into the device region as a mask, a step of depositing polycrystalline silicon on the entire surface, a step of forming a silicon dioxide film on the surface of the polycrystalline silicon, and a step of forming a silicon dioxide film on the silicon dioxide film. a step of forming a mask film having the shape of a non-element region, a step of etching away the silicon dioxide film using the mask film as a corrosion-resistant mask, a step of removing the mask film, and a step of removing the mask film having the shape of the non-element region thus formed. A step of etching away the polycrystalline silicon using a silicon dioxide film containing the silicon dioxide film as a corrosion-resistant mask, and removing the polycrystalline silicon, which is now located in the non-device region, and a silicon nitride film in the device region as a corrosion-resistant mask. a step of etching away the silicon dioxide film having the shape of the element region, and a step of completely oxidizing the polycrystalline silicon remaining in the non-device region after the previous process using the silicon nitride film having the shape of the element region as an oxidation-resistant mask. 1. A method of manufacturing an element isolation structure in a semiconductor device, the method comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP557380A JPS56103443A (en) | 1980-01-21 | 1980-01-21 | Production of element isolation structure for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP557380A JPS56103443A (en) | 1980-01-21 | 1980-01-21 | Production of element isolation structure for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56103443A JPS56103443A (en) | 1981-08-18 |
| JPS6310896B2 true JPS6310896B2 (en) | 1988-03-10 |
Family
ID=11614956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP557380A Granted JPS56103443A (en) | 1980-01-21 | 1980-01-21 | Production of element isolation structure for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56103443A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5873163A (en) * | 1981-10-27 | 1983-05-02 | Toshiba Corp | Mos semiconductor device |
| US4818235A (en) * | 1987-02-10 | 1989-04-04 | Industry Technology Research Institute | Isolation structures for integrated circuits |
| US4980311A (en) * | 1987-05-05 | 1990-12-25 | Seiko Epson Corporation | Method of fabricating a semiconductor device |
| US4927780A (en) * | 1989-10-02 | 1990-05-22 | Motorola, Inc. | Encapsulation method for localized oxidation of silicon |
| US6306726B1 (en) * | 1999-08-30 | 2001-10-23 | Micron Technology, Inc. | Method of forming field oxide |
-
1980
- 1980-01-21 JP JP557380A patent/JPS56103443A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56103443A (en) | 1981-08-18 |
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