JPH0116018B2 - - Google Patents
Info
- Publication number
- JPH0116018B2 JPH0116018B2 JP54119808A JP11980879A JPH0116018B2 JP H0116018 B2 JPH0116018 B2 JP H0116018B2 JP 54119808 A JP54119808 A JP 54119808A JP 11980879 A JP11980879 A JP 11980879A JP H0116018 B2 JPH0116018 B2 JP H0116018B2
- Authority
- JP
- Japan
- Prior art keywords
- type well
- well region
- conductivity type
- forming
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 239000012535 impurity Substances 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に係わるもので
あり、詳しては導電型の異なる２種類のウエル領
域の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing two types of well regions having different conductivity types.
従来のウエル領域の製造方法について、第１図
ａ〜ｄを用いて以下に説明する。第１図ａは、単
結晶シリコン基板１にシリコン酸化膜２を形成し
た半導体装置の断面図である。次に、Ｎ型ウエル
領域を形成するための窓をシリコン酸化膜２にホ
トエツチにより開け、レジスト４等をマスクとし
てＮ型を形成するイオン５をイオン注入しＮ型ウ
エル領域６を形成して第１図ｂとなる。このＮ型
ウエル領域を形成した後、レジスト４を剥離し、
そして第１図ｃのように再度シリコン酸化膜７を
形成する。シリコン酸化膜７は残存するシリコン
酸化膜３の上にも形成される。その後、パターン
化されたホトレジスト９をマスクとしてエツチン
グすることにより、Ｐ型ウエル領域を形成するた
めの窓を酸化膜８に開けた、次に、レジスト９等
をマスクとしてＰ型を形成するイオン１０をイオ
ン注入する。このようにして、第１図ｄに示すよ
うにＰ型ウエル領域１１を形成する。以上のよう
に、従来の方法はＮ型ウエル領域及びＰ型ウエル
領域をそれぞれ別のマスクを用いて形成してい
た。
A conventional method for manufacturing a well region will be described below with reference to FIGS. 1a to 1d. FIG. 1a is a cross-sectional view of a semiconductor device in which a silicon oxide film 2 is formed on a single crystal silicon substrate 1. Next, a window for forming an N-type well region is opened in the silicon oxide film 2 by photo-etching, and ions 5 for forming an N-type are implanted using a resist 4 as a mask to form an N-type well region 6. The result is shown in Figure 1b. After forming this N-type well region, the resist 4 is peeled off,
Then, as shown in FIG. 1c, a silicon oxide film 7 is formed again. The silicon oxide film 7 is also formed on the remaining silicon oxide film 3. Thereafter, a window for forming a P-type well region was opened in the oxide film 8 by etching using the patterned photoresist 9 as a mask. ion implantation. In this way, a P-type well region 11 is formed as shown in FIG. 1d. As described above, in the conventional method, the N-type well region and the P-type well region are formed using different masks.
又、従来のセルフアライン技術は特開昭52−
86083号公報の様に、フイールド絶縁膜とゲート
部とをマスクとしてソース・ドレイン領域を自己
整合的にイオンを打ち込んで形成し、チヤンネル
ストツパ領域とソース・ドレイン領域との境界面
にＰ−Ｎ接合を形成する方法である。 In addition, the conventional self-alignment technology was disclosed in Japanese Patent Application Laid-open No.
As in Publication No. 86083, the source/drain regions are formed by implanting ions in a self-aligned manner using the field insulating film and the gate portion as masks, and a P-N is formed at the interface between the channel stopper region and the source/drain region. This is a method of forming a bond.
〔本発明が解決しようとする問題点〕
しかし、従来のウエル領域の製造方法は、Ｎ型
ウエル領域及びＰ型ウエル領域をそれぞれ別のマ
スクを用いて形成していたので、
ホト工程が２回必要である
マスク合わせの誤差が大きいので、Ｎ型ウエ
ル領域とＰ型ウエル領域を隣接させることがで
きず、Ｎ型ウエル領域とＰ型ウエル領域は一定
距離はなして形成しなければならない
という問題点があつた。[Problems to be Solved by the Invention] However, in the conventional well region manufacturing method, the N-type well region and the P-type well region were formed using separate masks, so the photo process was performed twice. The problem is that the N-type well region and the P-type well region cannot be placed adjacent to each other due to the large error in mask alignment, and the N-type well region and the P-type well region must be formed at a certain distance apart. It was hot.
又、従来のセルフアライン法によると、
ソース・ドレイン領域は他の素子と結線する
ために複雑な形状となり、アラインメントマー
クとして用いることができない。 Furthermore, according to the conventional self-alignment method, the source/drain regions have complicated shapes because they are connected to other elements, and cannot be used as alignment marks.
イオン打ち込みでソース・ドレイン領域を形
成するためのマスクは、選択酸化法によつて形
成されたフイールド絶縁膜とゲート部であるた
め、高エネルギーを有するマスクを打ち込むと
ゲート部の絶縁性が破壊される欠点がある
隣接して形成された導電型の異なる２種類の
領域によつて作られるＰ−Ｎ接合面は、それぞ
れの不純物濃度が同一でないため、イオン打ち
込み後の熱拡散処理、PSG等の保護膜を形成
する工程での加熱処理等によつて、不純物濃度
の高い領域から低い領域へと移動し、セルフア
ライン法によつて形成されたＰ−Ｎ接合面をイ
オン打ち込みで形成した位置に止めておくこと
は難しいという欠点がある
という問題点があつた。 The mask used to form the source/drain regions by ion implantation is the field insulating film and gate area formed by selective oxidation, so implanting a mask with high energy will destroy the insulation of the gate area. The P-N junction surface, which is created by two adjacent regions of different conductivity types, does not have the same impurity concentration, so thermal diffusion treatment after ion implantation, PSG, etc. Due to heat treatment etc. in the process of forming the protective film, the impurity concentration is moved from a region with a high concentration to a region with a low concentration, and the P-N junction surface formed by the self-alignment method is moved to the position formed by ion implantation. The problem was that it was difficult to stop it.
以上のように、従来の技術では導電型の異なる
２種類の領域を深い拡散層にしそして隣接して形
成し、そのＰ−Ｎ接合面を後工程の加熱条件によ
らず一定位置に止める方法がなく、半導体装置の
高密度化、低コスト化及び高性能化の隘路となて
いた。 As described above, in the conventional technology, two types of regions with different conductivity types are formed into deep diffusion layers and are formed adjacent to each other, and the P-N junction surface is held at a fixed position regardless of the heating conditions in the subsequent process. This has been a bottleneck in increasing the density, lowering costs, and improving the performance of semiconductor devices.
そこで、本発明はこのような問題点を解決する
ものであり、その目的とするところは
半導体装置を高密度化する
ホト工程を短縮する
ことを同時に達成する製造方法を提供することに
ある。 SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a manufacturing method that simultaneously increases the density of a semiconductor device and shortens the photo process.
本発明は、半導体基板に第１導電型ウエル及び
第２導電型ウエルを形成した後、前記第１導電型
ウエル及び前記第２導電型ウエルに能動素子、受
動素子を形成する半導体装置の製造方法におい
て、前記半導体基板上に酸化に対してマスク作用
を有する耐酸化膜を選択的に形成する工程、前記
耐酸化膜を形成した部分をマスクとして前記半導
体基板中に第１導電型のイオンを導入することに
より前記第１導電型ウエル領域を形成する工程、
前記耐酸化膜をマスクとして前記第１導電型ウエ
ル領域を選択酸化し、前記第１導電型ウエル領域
上に選択酸化膜を形成する工程、前記耐酸化膜を
エツチング除去する工程と前記選択酸化膜をマス
クとして前記半導体基板中に第２導電型のイオン
を導入することにより前記第１導電型ウエル領域
に隣接して前記第２導電型ウエル領域を形成する
工程を有することを特徴とする。
The present invention provides a method for manufacturing a semiconductor device, in which a first conductivity type well and a second conductivity type well are formed in a semiconductor substrate, and then active elements and passive elements are formed in the first conductivity type well and the second conductivity type well. selectively forming an oxidation-resistant film having a masking effect against oxidation on the semiconductor substrate, introducing ions of a first conductivity type into the semiconductor substrate using the portion where the oxidation-resistant film is formed as a mask; forming the first conductivity type well region by;
Selectively oxidizing the first conductivity type well region using the oxidation resistant film as a mask to form a selective oxide film on the first conductivity type well region, etching away the oxidation resistant film, and the selective oxide film. The method is characterized by comprising a step of forming the second conductivity type well region adjacent to the first conductivity type well region by introducing second conductivity type ions into the semiconductor substrate using the mask as a mask.
第２図ｂに示すように、イオン打ち込みに対す
るマスク１５，１６及び１７は厚さが厚いので、
高エネルギーのイオン打ち込みによりイオンがそ
れらを突き抜けることがなく、イオン１８によつ
て深いＮ型ウエル領域を形成できる。また、第２
図ｄに示すように、選択酸化膜２１は厚さが厚い
ので、高エネルギーのイオン打ち込みによりイオ
ンがそれを突き抜けＮ型ウエル領域に達すること
なく、イオン２２によつて深いＰ型ウエル領域を
形成できる。
As shown in FIG. 2b, since the masks 15, 16 and 17 for ion implantation are thick,
High-energy ion implantation prevents ions from penetrating them, allowing the ions 18 to form deep N-type well regions. Also, the second
As shown in Figure d, since the selective oxide film 21 is thick, ions do not penetrate through it and reach the N-type well region by high-energy ion implantation, and a deep P-type well region is formed by the ions 22. can.
又、Ｐ型ウエル領域とＮ型ウエル領域とが接し
て形成されるＰ−Ｎ接合面は、それぞれの領域の
不純物濃度が加熱によつて移動しない程度に等し
いので、後工程の加熱条件によるＰ−Ｎ接合面の
移動を防止することができる。 In addition, since the P-N junction surface formed by the contact between the P-type well region and the N-type well region is such that the impurity concentration in each region is equal to the extent that it does not shift due to heating, -N movement of the joint surface can be prevented.
このような不純物濃度が略等しい導電型の異な
る２種類のウエル領域を選択酸化法を用いて形成
することにより、実己整合なイオン打ち込みとジ
ヤンクションを正確な位置に形成することの他
に、ジヤンクションの幅のバラツキを小さくする
こと、ジヤンクションにおける不純物分布バラツ
キを小さくすること及び選択酸化膜のバーズビー
クと不純物の熱拡散を利用した緩らかな不純物の
分布等が可能になる。 By forming two types of well regions with substantially equal impurity concentrations and different conductivity types using a selective oxidation method, in addition to forming self-aligned ion implantation and junction at accurate positions, It is possible to reduce variations in junction width, to reduce variations in impurity distribution at junctions, and to achieve gentle impurity distribution by utilizing the bird's beak of the selective oxide film and thermal diffusion of impurities.
第２図ａ〜ｄは、本発明の１実施例における代
表的な工程に係わる図である。
FIGS. 2a to 2d are diagrams relating to typical steps in one embodiment of the present invention.
第２図ａは、単結晶シリコン基板１２にシリコ
ン酸化膜１３及び従来から良く知られているよう
に、酸化に対してマスク作用を有する耐酸化マス
クとなりえるシリコン窒化膜１４を形成したもの
である。次に、レジスト１６を塗布し露光しエツ
チングすることにより、マスクの形状に形成され
たレジスト１７が形成される。レジスト１７をマ
スクとして、Ｎ型ウエル領域を形成するための窓
をエツチングにより明け、シリコン窒化膜１６及
びレジスト１７をマスクとしてＮ型を形成するイ
オン１８をイオン注入し、第２図ｂに示すように
Ｎ型ウエル領域１９を形成する。次に、シリコン
窒化膜６をマスクとして選択酸化を行い第２図ｃ
のようにシリコン酸化膜２０を形成する。その
後、シリコン窒化膜をエツチング除去すると選択
酸化した部分のシリコン酸化膜２１が残る。この
シリコン酸化膜２１をマスクとしてＰ型を形成す
るイオン２２を注入することにより、第２図のよ
うにＰ型ウエル領域２３を形成する。この後の工
程については、通常の方法で、第２図ｄのシリコ
ン酸化膜２１をエツチング除去しＰ型ウエル領域
２３の表面を露出させ、Ｎ型ウエル領域とＰ型ウ
エル領域を隣接させて形成する。これらのウエル
領域に能動素子としてトランジスタ、ダイオード
等、受動素子としてレジスト、キヤパシタ等を形
成し半導体装置を製造する。 In FIG. 2a, a silicon oxide film 13 and a silicon nitride film 14, which can serve as an oxidation-resistant mask having a masking effect against oxidation, are formed on a single-crystal silicon substrate 12, as is well known in the art. . Next, a resist 16 is applied, exposed, and etched to form a resist 17 in the shape of a mask. Using the resist 17 as a mask, a window for forming an N-type well region is opened by etching, and using the silicon nitride film 16 and resist 17 as a mask, ions 18 for forming an N-type well are implanted, as shown in FIG. 2b. An N-type well region 19 is formed therein. Next, selective oxidation is performed using the silicon nitride film 6 as a mask, as shown in FIG.
A silicon oxide film 20 is formed as shown in FIG. Thereafter, when the silicon nitride film is removed by etching, the selectively oxidized portions of the silicon oxide film 21 remain. Using this silicon oxide film 21 as a mask, ions 22 forming a P type are implanted to form a P type well region 23 as shown in FIG. In the subsequent steps, the silicon oxide film 21 shown in FIG. do. In these well regions, active elements such as transistors and diodes, and passive elements such as resists and capacitors are formed to manufacture semiconductor devices.
以上述べたように、本願発明は
Ｎ型ウエル領域とＰ型ウエル領域を隣接して
形成し、そのＰ−Ｎ接合面を後工程の加熱条件
によらず一定位置に止めることができた
更に言及すれば、ソース・ドレイン拡散層、
フイールド拡散層及びウエル領域の不純物濃度
は、それぞれ、1020〜1022、1018〜1019及び1015
〜1016であり、セルフアラインでソース・ドレ
イン拡散層を形成するとその境界はフイールド
拡散層の中に拡がつていくのに対し、セルフア
ラインでウエル領域を形成すると隣接するウエ
ル領域の不純物濃度が同程度なのでウエル領域
の境界は移動しない。加えるに、ソース・ドレ
イン拡散層の深さは1μm前後、ウエル領域の深
さは4μm前後であり、このように拡散を深く行
う場合は、深さ方向以外に横方向にも大きく拡
散が行われるため、セルフアラインでウエル領
域を形成することはソース・ドレイン拡散層の
セルフアラインと比較し格段に形状精度の高い
拡散ができる。このことにより、ウエル領域の
境界のバラツキについて考慮する必要がなくな
り、周辺部までトランジスタ等を形成でき半導
体装置の高密度が可能になつた。
As described above, in the present invention, the N-type well region and the P-type well region are formed adjacent to each other, and the P-N junction surface can be fixed at a fixed position regardless of the heating conditions in the subsequent process. Then, the source/drain diffusion layer,
The impurity concentrations of the field diffusion layer and well region are 10 20 to 10 22 , 10 18 to 10 19 and 10 15 , respectively.
~10 16 , and when a source/drain diffusion layer is formed by self-alignment, the boundary spreads into the field diffusion layer, whereas when a well region is formed by self-alignment, the impurity concentration of the adjacent well region increases. Since they are of the same extent, the boundaries of the well regions do not move. In addition, the depth of the source/drain diffusion layer is around 1 μm, and the depth of the well region is around 4 μm, so when diffusion is performed deep like this, the diffusion is large not only in the depth direction but also in the lateral direction. Therefore, forming the well region by self-alignment allows diffusion with much higher shape accuracy than self-alignment of the source/drain diffusion layer. This eliminates the need to consider variations in the boundaries of well regions, and allows transistors and the like to be formed up to the periphery, making it possible to fabricate semiconductor devices with high density.
Ｐ型ウエル領域とＮ型ウエル領域が隣接して
形成され、集積度を従来の製造方法に比して20
〜30％改善することができた
Ｎ型ウエル領域に形成されたソース、ドレイ
ン又はゲートとＰ型ウエル領域に形成されたソ
ース、ドレイン又はゲートとの配線距離を10〜
40％短くすることができ、配線抵抗及び配線に
帰因する寄生容量を大幅に小さくすることがで
きた
Ｐ型ウエル領域とＮ型ウエル領域の表面の境
界に形成した段差をアラインメントマークとし
て用い精度の高いマスク合わせができた。 A P-type well region and an N-type well region are formed adjacent to each other, reducing the degree of integration by 20% compared to conventional manufacturing methods.
The wiring distance between the source, drain, or gate formed in the N-type well region and the source, drain, or gate formed in the P-type well region was improved by ~30%.
The wiring resistance and parasitic capacitance caused by the wiring could be significantly reduced by 40%. Accuracy is achieved by using the step formed at the boundary between the surfaces of the P-type well region and the N-type well region as an alignment mark. I was able to match the mask with a high quality.
Ｐ型ウエル領域及びＮ型ウエル領域を形成す
るのに、ホトエツチ工程を従来の２回から１回
へと50％減らすことができた
という効果を有する。 This has the advantage that the number of photo-etching steps required for forming the P-type well region and the N-type well region can be reduced by 50% from the conventional two to one.
第１図ａ〜ｄはウエル領域を形成する従来の製
造方法の主要工程における半導体装置の断面図、
第２図ａ〜ｄは本発明の１実施例を示す主要工程
における半導体装置の断面図である。
１２……単結晶シリコン基板、１３，１５，２
０，２１……シリコン酸化膜、１４，１６……シ
リコン窒化膜、１８……Ｎ型を形成するイオン、
１９……Ｎ型ウエル領域、２２……Ｐ型を形成す
るイオン、２３……Ｐ型ウエル領域。
1A to 1D are cross-sectional views of a semiconductor device in main steps of a conventional manufacturing method for forming a well region;
FIGS. 2a to 2d are cross-sectional views of a semiconductor device in main steps, showing one embodiment of the present invention. 12... Single crystal silicon substrate, 13, 15, 2
0, 21... silicon oxide film, 14, 16... silicon nitride film, 18... ion forming N type,
19... N type well region, 22... Ions forming P type, 23... P type well region.
Claims (1)
型ウエルを形成した後、能動素子、受動素子を前
記第１導電型ウエル及び前記第２導電型ウエルに
形成する半導体装置の製造方法において、前記半
導体基板上に酸化に対してマスク作用を有する耐
酸化膜を選択的に形成する工程、前記耐酸化膜を
形成した部分をマスクとして前記半導体基板中に
第１導電型のイオンを導入することにより前記第
１導電型ウエル領域を形成する工程、前記耐酸化
膜をマスクとして前記第１導電型ウエル領域を選
択酸化し、前記第１導電型ウエル領域上に選択酸
化膜を形成する工程、前記耐酸化膜をエツチング
除去する工程と前記選択酸化膜をマスクとして前
記半導体基板中に第２導電型のイオンを導入する
ことにより前記第１導電型ウエル領域に隣接して
前記第２導電型ウエル領域を形成する工程を有す
ることを特徴とする半導体装置の製造方法。1. A method for manufacturing a semiconductor device in which a first conductivity type well and a second conductivity type well are formed in a semiconductor substrate, and then an active element and a passive element are formed in the first conductivity type well and the second conductivity type well, A step of selectively forming an oxidation-resistant film having a masking effect against oxidation on a semiconductor substrate, by introducing ions of a first conductivity type into the semiconductor substrate using the portion where the oxidation-resistant film is formed as a mask. forming the first conductivity type well region, selectively oxidizing the first conductivity type well region using the oxidation resistant film as a mask, and forming a selective oxidation film on the first conductivity type well region; The second conductivity type well region is formed adjacent to the first conductivity type well region by etching away the oxide film and introducing second conductivity type ions into the semiconductor substrate using the selective oxide film as a mask. 1. A method of manufacturing a semiconductor device, comprising a step of forming a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11980879A JPS5643756A (en) | 1979-09-18 | 1979-09-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11980879A JPS5643756A (en) | 1979-09-18 | 1979-09-18 | Manufacture of semiconductor device |
Related Child Applications (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62146385A Division JPS63147A (en) | 1987-06-12 | 1987-06-12 | Semiconductor device |
| JP62146384A Division JPS63146A (en) | 1987-06-12 | 1987-06-12 | Semiconductor device |
| JP1341850A Division JPH02224269A (en) | 1989-12-29 | 1989-12-29 | Semiconductor device |
| JP1341849A Division JP2572653B2 (en) | 1989-12-29 | 1989-12-29 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5643756A JPS5643756A (en) | 1981-04-22 |
| JPH0116018B2 true JPH0116018B2 (en) | 1989-03-22 |
Family
ID=14770733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11980879A Granted JPS5643756A (en) | 1979-09-18 | 1979-09-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5643756A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3133468A1 (en) * | 1981-08-25 | 1983-03-17 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING HIGHLY INTEGRATED COMPLEMENTARY MOS FIELD EFFECT TRANSISTOR CIRCUITS IN SILICON GATE TECHNOLOGY |
| DE3149185A1 (en) * | 1981-12-11 | 1983-06-23 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR THE PRODUCTION OF NEIGHBORS WITH DOPE IMPLANTED TANKS IN THE PRODUCTION OF HIGHLY INTEGRATED COMPLEMENTARY MOS FIELD EFFECT TRANSISTOR CIRCUITS |
| JPS6031276A (en) * | 1983-07-29 | 1985-02-18 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS6144456A (en) * | 1984-08-09 | 1986-03-04 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS63119250A (en) * | 1987-10-23 | 1988-05-23 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH02338A (en) * | 1988-12-16 | 1990-01-05 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| JPH02337A (en) * | 1988-12-16 | 1990-01-05 | Hitachi Ltd | Manufacture of semiconductor integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5286083A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Production of complimentary isolation gate field effect transistor |
| JPS5375781A (en) * | 1976-12-14 | 1978-07-05 | Standard Microsyst Smc | Method of producing mos semiconductor circuit |
-
1979
- 1979-09-18 JP JP11980879A patent/JPS5643756A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5286083A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Production of complimentary isolation gate field effect transistor |
| JPS5375781A (en) * | 1976-12-14 | 1978-07-05 | Standard Microsyst Smc | Method of producing mos semiconductor circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5643756A (en) | 1981-04-22 |
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