JPS56103443A - Production of element isolation structure for semiconductor device - Google Patents

Production of element isolation structure for semiconductor device

Info

Publication number
JPS56103443A
JPS56103443A JP557380A JP557380A JPS56103443A JP S56103443 A JPS56103443 A JP S56103443A JP 557380 A JP557380 A JP 557380A JP 557380 A JP557380 A JP 557380A JP S56103443 A JPS56103443 A JP S56103443A
Authority
JP
Japan
Prior art keywords
film
poly
layer
sio2 film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP557380A
Other languages
Japanese (ja)
Other versions
JPS6310896B2 (en
Inventor
Toshiyuki Ishijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP557380A priority Critical patent/JPS56103443A/en
Publication of JPS56103443A publication Critical patent/JPS56103443A/en
Publication of JPS6310896B2 publication Critical patent/JPS6310896B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To achieve integration at a high level by forming an oxide for isolating elements preventing infiltration into the element region. CONSTITUTION:An Si3N4 film 23 is laid on an SiO2 film 22 on a P type Si substrate and with a resist mask applied, the films 23 and 22 and the substrate surface are etched sequentially. Then, after the removal of the resist, B ion is injected to form a P<+> layer 26. Then, covered with a poly Si27, a thermal oxide film 28 is formed and a resist mask 29 is applied. The SiO2 film 28 and the body poly Si27 are etched sequentially thereby making the surface of the Si3N4 film 23' almost flush with the end face of the poly Si layer 27'. Subsequently, the SiO2 film 28' is etched and the poly Si27 is oxidized completely to form a thick SiO2 film 27a in a nonelement region. Thus, an isolation layer is completed. With such an arrangement, a step is formed between a P<+> channel stopper and an N layer formed in the element region thereby allowing less floating capacity. This prevents bird beak to form a highly integrated semiconductor device.
JP557380A 1980-01-21 1980-01-21 Production of element isolation structure for semiconductor device Granted JPS56103443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP557380A JPS56103443A (en) 1980-01-21 1980-01-21 Production of element isolation structure for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP557380A JPS56103443A (en) 1980-01-21 1980-01-21 Production of element isolation structure for semiconductor device

Publications (2)

Publication Number Publication Date
JPS56103443A true JPS56103443A (en) 1981-08-18
JPS6310896B2 JPS6310896B2 (en) 1988-03-10

Family

ID=11614956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP557380A Granted JPS56103443A (en) 1980-01-21 1980-01-21 Production of element isolation structure for semiconductor device

Country Status (1)

Country Link
JP (1) JPS56103443A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873163A (en) * 1981-10-27 1983-05-02 Toshiba Corp Mos semiconductor device
US4818235A (en) * 1987-02-10 1989-04-04 Industry Technology Research Institute Isolation structures for integrated circuits
US4927780A (en) * 1989-10-02 1990-05-22 Motorola, Inc. Encapsulation method for localized oxidation of silicon
US4980311A (en) * 1987-05-05 1990-12-25 Seiko Epson Corporation Method of fabricating a semiconductor device
US6306726B1 (en) * 1999-08-30 2001-10-23 Micron Technology, Inc. Method of forming field oxide

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873163A (en) * 1981-10-27 1983-05-02 Toshiba Corp Mos semiconductor device
US4818235A (en) * 1987-02-10 1989-04-04 Industry Technology Research Institute Isolation structures for integrated circuits
US4980311A (en) * 1987-05-05 1990-12-25 Seiko Epson Corporation Method of fabricating a semiconductor device
US4927780A (en) * 1989-10-02 1990-05-22 Motorola, Inc. Encapsulation method for localized oxidation of silicon
US6306726B1 (en) * 1999-08-30 2001-10-23 Micron Technology, Inc. Method of forming field oxide
US6326672B1 (en) 1999-08-30 2001-12-04 Micron Technology, Inc. LOCOS fabrication processes and semiconductive material structures

Also Published As

Publication number Publication date
JPS6310896B2 (en) 1988-03-10

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