JPS56140641A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56140641A
JPS56140641A JP4298380A JP4298380A JPS56140641A JP S56140641 A JPS56140641 A JP S56140641A JP 4298380 A JP4298380 A JP 4298380A JP 4298380 A JP4298380 A JP 4298380A JP S56140641 A JPS56140641 A JP S56140641A
Authority
JP
Japan
Prior art keywords
groove
si3n4
sio2
selective oxidation
active region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4298380A
Other languages
Japanese (ja)
Other versions
JPS6358370B2 (en
Inventor
Osamu Ishikawa
Takeya Ezaki
Masabumi Kubota
Kosei Kajiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4298380A priority Critical patent/JPS56140641A/en
Publication of JPS56140641A publication Critical patent/JPS56140641A/en
Publication of JPS6358370B2 publication Critical patent/JPS6358370B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To prevent lateral spread of an oxide film at selective oxidation and to obtain high density, by providing a groove on the outside of an active region and filling it by a nitride film and the oxide film. CONSTITUTION:The groove 12 is formed around the periphery of the active region of an Si substrate 11 by sputter etching so as to obtain a rectangular cross section. Si3N4 13 and SiO2 14 are layered on all the surface and the groove is completely buried. The films 14 and 13 on the outside of the groove and the active region are etched out, and an SiO2 thick film 16 is formed by the selective oxidation with the remained Si3N4 13' as a mask. Si3N4 13' is removed. In this constitution, buried SiO2 14' and Si3N4 13 block the lateral spread of SiO2, lattice defects 17 due to stress at the selective oxidation are generated only at the groove wall on the side opposite to the active layer and at the bottom of the groove, and the effect to the active layer scarcely exist.
JP4298380A 1980-04-01 1980-04-01 Manufacture of semiconductor device Granted JPS56140641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4298380A JPS56140641A (en) 1980-04-01 1980-04-01 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4298380A JPS56140641A (en) 1980-04-01 1980-04-01 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS56140641A true JPS56140641A (en) 1981-11-04
JPS6358370B2 JPS6358370B2 (en) 1988-11-15

Family

ID=12651266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4298380A Granted JPS56140641A (en) 1980-04-01 1980-04-01 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56140641A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5972740A (en) * 1982-10-19 1984-04-24 Nec Corp Semiconductor integrated circuit device and manufacture thereof
JPH0232551A (en) * 1988-07-22 1990-02-02 Sony Corp Semiconductor device
US5899727A (en) * 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5981357A (en) * 1996-04-10 1999-11-09 Advanced Micro Devices, Inc. Semiconductor trench isolation with improved planarization methodology

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2606428B2 (en) * 1990-09-21 1997-05-07 ティアツク株式会社 Disk drive head carriage

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244584A (en) * 1975-10-06 1977-04-07 Matsushita Electric Ind Co Ltd Method of treating semiconductor substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244584A (en) * 1975-10-06 1977-04-07 Matsushita Electric Ind Co Ltd Method of treating semiconductor substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5972740A (en) * 1982-10-19 1984-04-24 Nec Corp Semiconductor integrated circuit device and manufacture thereof
JPH0232551A (en) * 1988-07-22 1990-02-02 Sony Corp Semiconductor device
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
US5981357A (en) * 1996-04-10 1999-11-09 Advanced Micro Devices, Inc. Semiconductor trench isolation with improved planarization methodology
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5899727A (en) * 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US6353253B2 (en) 1996-05-02 2002-03-05 Advanced Micro Devices, Inc. Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

Also Published As

Publication number Publication date
JPS6358370B2 (en) 1988-11-15

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