JPS5772346A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5772346A
JPS5772346A JP14894180A JP14894180A JPS5772346A JP S5772346 A JPS5772346 A JP S5772346A JP 14894180 A JP14894180 A JP 14894180A JP 14894180 A JP14894180 A JP 14894180A JP S5772346 A JPS5772346 A JP S5772346A
Authority
JP
Japan
Prior art keywords
film
depressions
entire surface
levelled
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14894180A
Other languages
Japanese (ja)
Other versions
JPS6250978B2 (en
Inventor
Akira Kurosawa
Takahiko Moriya
Riyouichi Hazuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14894180A priority Critical patent/JPS5772346A/en
Publication of JPS5772346A publication Critical patent/JPS5772346A/en
Publication of JPS6250978B2 publication Critical patent/JPS6250978B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Abstract

PURPOSE:To make it possible to obtain high density integration of extremely fine elements, by providing depressions on the surface of a semiconductor substrate in a field section, providing an insulating film on the entire surface, levelling off the entire surface and filling the depressions with the insulating film in such a manner that the surface is almost levelled off. CONSTITUTION:A silicon oxide film 12 is formed on a P type silicon substrate 11, and the film 12 on a field region is etched leaving the film 12 on an element forming region untouched. And then, with the film 12 as a mask, the substrate 11 is etched to form depressions 13. And, a field reversion preventing layer 14 is formed by using the film 12 as a mask, and then, the film 12 is removed later. And then, a thermally oxidized film 15 is newly formed on the entire surface, and a silicon nitride film 16 is attached to a thickness of approximately 1.5mum by plasma gaseous growth process. And then, surface layer of the film 16 is removed by approximately 1mum to obtain a levelled surface for the film 16. And, etching is continued until the film 15 is exposed.
JP14894180A 1980-10-24 1980-10-24 Manufacture of semiconductor device Granted JPS5772346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14894180A JPS5772346A (en) 1980-10-24 1980-10-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14894180A JPS5772346A (en) 1980-10-24 1980-10-24 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5772346A true JPS5772346A (en) 1982-05-06
JPS6250978B2 JPS6250978B2 (en) 1987-10-28

Family

ID=15464080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14894180A Granted JPS5772346A (en) 1980-10-24 1980-10-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5772346A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5913334A (en) * 1982-07-01 1984-01-24 コミツサレ・ア・レナジイ・アトミツク Method of producing oxidized film of integrated circuit
JPS6428925A (en) * 1987-07-24 1989-01-31 Semiconductor Energy Lab Formation of insulating film

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6442163U (en) * 1987-09-09 1989-03-14
JP6498022B2 (en) 2015-04-22 2019-04-10 東京エレクトロン株式会社 Etching method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5913334A (en) * 1982-07-01 1984-01-24 コミツサレ・ア・レナジイ・アトミツク Method of producing oxidized film of integrated circuit
JPS6428925A (en) * 1987-07-24 1989-01-31 Semiconductor Energy Lab Formation of insulating film

Also Published As

Publication number Publication date
JPS6250978B2 (en) 1987-10-28

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