JPS57199231A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57199231A
JPS57199231A JP8385381A JP8385381A JPS57199231A JP S57199231 A JPS57199231 A JP S57199231A JP 8385381 A JP8385381 A JP 8385381A JP 8385381 A JP8385381 A JP 8385381A JP S57199231 A JPS57199231 A JP S57199231A
Authority
JP
Japan
Prior art keywords
deposited
film
sio2 film
sio2
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8385381A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Shinada
Akira Kurosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8385381A priority Critical patent/JPS57199231A/en
Publication of JPS57199231A publication Critical patent/JPS57199231A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Abstract

PURPOSE:To suppress bird's beak and realize high integration, by a method wherein SiO2 film is deposited in isolation region and then buried so as to form flat surface with element forming region. CONSTITUTION:N<+> type buried layer 2 and P type channel cut region 3 are formed on P<-> type Si substrate 1, and then N type epitaxial layer 4 is provided and isolation region is etched using a mask 5. Plasma CVD-SiO2 film 6 deposited on whole surface, and SiO2 film in stepped side surface is removed by etching process. The mask 5 together with SiO2 film thereon is removed in liftoff pocess, and a thermal oxide film 7 is formed on surface of the epitaxial layer 4. CVD-SiO2 film 8 is deposited on whole surface and a groove is filled, and a resist film 9 is deposited thereon and the surface is made flat. The films 9, 8 are uniformly etched and SiO2 surface in element forming region is exposed.
JP8385381A 1981-06-02 1981-06-02 Manufacture of semiconductor device Pending JPS57199231A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8385381A JPS57199231A (en) 1981-06-02 1981-06-02 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8385381A JPS57199231A (en) 1981-06-02 1981-06-02 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57199231A true JPS57199231A (en) 1982-12-07

Family

ID=13814245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8385381A Pending JPS57199231A (en) 1981-06-02 1981-06-02 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57199231A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4679299A (en) * 1986-08-11 1987-07-14 Ncr Corporation Formation of self-aligned stacked CMOS structures by lift-off

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4679299A (en) * 1986-08-11 1987-07-14 Ncr Corporation Formation of self-aligned stacked CMOS structures by lift-off

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